Icestorm: AESD measurements

Code:

  aesd v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  aesd v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	202	20082	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10003	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20086	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10

Test 3: Latency 1->2

Code:

  aesd v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	769247	10131	200	10043	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10003	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	22	20082	2	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	0	30	0	768905	10010	20	0	10000	20	20000	1	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  aesd v0.16b, v8.16b
  movi v1.16b, 0
  aesd v1.16b, v8.16b
  movi v2.16b, 0
  aesd v2.16b, v8.16b
  movi v3.16b, 0
  aesd v3.16b, v8.16b
  movi v4.16b, 0
  aesd v4.16b, v8.16b
  movi v5.16b, 0
  aesd v5.16b, v8.16b
  movi v6.16b, 0
  aesd v6.16b, v8.16b
  movi v7.16b, 0
  aesd v7.16b, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40539	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40115	80109	101	80008	100	80012	300	320056	80113	200	80013	200	160024	1	160000	100
160204	40091	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	300	320184	80145	200	80045	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160090	1	160000	100
160204	40112	80109	101	80008	100	80012	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160090	1	160000	100
160204	40091	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5057

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43981	80020	11	80009	10	80013	30	320056	80023	20	80013	20	160000	1	160000	10
160024	41276	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40381	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40451	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40441	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40461	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40451	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40451	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40451	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160092	1	160000	10
160024	40530	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  aesd v0.16b, v16.16b
  aesd v1.16b, v16.16b
  aesd v2.16b, v16.16b
  aesd v3.16b, v16.16b
  aesd v4.16b, v16.16b
  aesd v5.16b, v16.16b
  aesd v6.16b, v16.16b
  aesd v7.16b, v16.16b
  aesd v8.16b, v16.16b
  aesd v9.16b, v16.16b
  aesd v10.16b, v16.16b
  aesd v11.16b, v16.16b
  aesd v12.16b, v16.16b
  aesd v13.16b, v16.16b
  aesd v14.16b, v16.16b
  aesd v15.16b, v16.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80109	160107	101	160006	100	160010	300	640284	160170	200	160073	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320152	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320152	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320146	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640288	160171	200	160076	200	320030	1	160000	100
160205	80088	160168	101	160067	100	160071	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80391	160017	11	160006	10	160010	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80038	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320122	1	160000	10
160024	80039	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10

AESD

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations