Icestorm: AESD + AESIMC measurements

Code:

  aesd v0.16b, v1.16b
  aesimc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
2004	3037	1003	1	1002	1002	75905	1000	2000	14365	12102	3177	6397	6152	2089	8978
2004	3039	1004	1	1003	1003	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0
2004	3033	1001	1	1000	1000	75905	1000	2000	0	0	3000	1	0	2000	0

Test 2: Latency 1->1

Code:

  aesd v0.16b, v1.16b
  aesimc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	30037	10103	101	10002	100	10002	300	768905	10100	200	20006	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	30037	10013	11	10002	10	10002	30	768905	10010	20	20006	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10

Test 3: Latency 1->2

Code:

  aesd v0.16b, v0.16b
  aesimc v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20004	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  aesd v0.16b, v8.16b
  aesimc v0.16b, v0.16b
  movi v1.16b, 0
  aesd v1.16b, v8.16b
  aesimc v1.16b, v1.16b
  movi v2.16b, 0
  aesd v2.16b, v8.16b
  aesimc v2.16b, v2.16b
  movi v3.16b, 0
  aesd v3.16b, v8.16b
  aesimc v3.16b, v3.16b
  movi v4.16b, 0
  aesd v4.16b, v8.16b
  aesimc v4.16b, v4.16b
  movi v5.16b, 0
  aesd v5.16b, v8.16b
  aesimc v5.16b, v5.16b
  movi v6.16b, 0
  aesd v6.16b, v8.16b
  aesimc v6.16b, v6.16b
  movi v7.16b, 0
  aesd v7.16b, v8.16b
  aesimc v7.16b, v7.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240204	80496	80134	101	80033	100	80035	300	320026	80106	200	160012	200	240084	1	240000	100
240205	80095	80135	101	80034	100	80048	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320030	80107	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240205	80071	80135	101	80034	100	80047	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0216

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240024	84144	80271	11	80260	10	80262	30	320770	80202	20	160000	20	240000	1	240000	10
240024	82855	80197	11	80186	10	80186	30	320489	80130	20	160000	20	240000	1	240000	10
240024	81676	80127	11	80116	10	80116	30	320464	80125	20	160000	20	240000	1	240000	10
240025	82191	80186	11	80175	10	80192	30	320469	80127	20	160000	20	240000	1	240000	10
240024	81844	80129	11	80118	10	80118	30	320767	80185	20	160056	20	240000	1	240000	10
240024	81782	80133	11	80122	10	80122	30	320489	80129	20	160000	20	240000	1	240000	10
240024	81695	80128	11	80117	10	80117	30	320493	80130	20	160000	20	240000	1	240000	10
240024	81689	80128	11	80117	10	80117	30	320476	80128	20	160000	20	240000	1	240000	10
240024	81679	80129	11	80118	10	80118	30	320476	80127	20	160000	20	240000	1	240000	10
240024	81690	80128	11	80117	10	80117	30	320464	80126	20	160000	20	240000	1	240000	10

Test 5: throughput

Count: 16

Code:

  aesd v0.16b, v16.16b
  aesimc v0.16b, v0.16b
  aesd v1.16b, v16.16b
  aesimc v1.16b, v1.16b
  aesd v2.16b, v16.16b
  aesimc v2.16b, v2.16b
  aesd v3.16b, v16.16b
  aesimc v3.16b, v3.16b
  aesd v4.16b, v16.16b
  aesimc v4.16b, v4.16b
  aesd v5.16b, v16.16b
  aesimc v5.16b, v5.16b
  aesd v6.16b, v16.16b
  aesimc v6.16b, v6.16b
  aesd v7.16b, v16.16b
  aesimc v7.16b, v7.16b
  aesd v8.16b, v16.16b
  aesimc v8.16b, v8.16b
  aesd v9.16b, v16.16b
  aesimc v9.16b, v9.16b
  aesd v10.16b, v16.16b
  aesimc v10.16b, v10.16b
  aesd v11.16b, v16.16b
  aesimc v11.16b, v11.16b
  aesd v12.16b, v16.16b
  aesimc v12.16b, v12.16b
  aesd v13.16b, v16.16b
  aesimc v13.16b, v13.16b
  aesd v14.16b, v16.16b
  aesimc v14.16b, v14.16b
  aesd v15.16b, v16.16b
  aesimc v15.16b, v15.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
320204	80908	160110	101	160009	0	100	160013	0	300	0	640052	160112	200	0	320024	200	480036	1	320000	100
320204	80139	160109	101	160008	0	100	160012	0	300	0	640052	160112	200	0	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	0	100	160012	0	300	0	640052	160112	200	0	320024	200	480039	1	320000	100
320204	80089	160109	101	160008	0	100	160012	0	300	0	640052	160112	200	0	320024	200	480138	1	320000	100
320204	80100	160110	101	160009	0	100	160013	0	300	0	640056	160113	200	0	320026	200	480036	1	320000	100
320204	80136	160110	101	160009	0	100	160013	0	300	0	640056	160113	200	0	320026	200	480138	1	320000	100
320204	80102	160110	101	160009	0	100	160013	0	300	0	640052	160112	200	0	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	0	100	160012	0	300	0	640052	160112	200	0	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	0	100	160012	0	300	0	640052	160112	200	0	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	0	100	160012	0	300	0	640052	160112	200	0	320024	200	480036	1	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5418

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320024	87525	160020	11	160009	10	160013	30	640056	160023	20	320026	20	0	480000	1	0	320000	10
320024	87451	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10
320024	86688	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10
320024	86686	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10
320024	86697	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480138	1	0	320000	10
320024	86720	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10
320024	86794	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10
320024	86937	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10
320024	86801	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10
320024	86836	160011	11	160000	10	160000	30	640000	160010	20	320000	20	0	480000	1	0	320000	10

AESD + AESIMC

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations