Icestorm: AESE measurements

Code:

  aese v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  aese v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10003	200	0	20006	1	0	10000	100
10204	30033	10101	101	10000	100	10000	307	769162	10133	202	10041	200	0	20006	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10003	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20086	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10

Test 3: Latency 1->2

Code:

  aese v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	307	771089	10234	202	10161	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10003	200	20006	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10
10024	30033	10011	11	10000	10	10000	30	768905	10010	20	10000	20	20000	1	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  aese v0.16b, v8.16b
  movi v1.16b, 0
  aese v1.16b, v8.16b
  movi v2.16b, 0
  aese v2.16b, v8.16b
  movi v3.16b, 0
  aese v3.16b, v8.16b
  movi v4.16b, 0
  aese v4.16b, v8.16b
  movi v5.16b, 0
  aese v5.16b, v8.16b
  movi v6.16b, 0
  aese v6.16b, v8.16b
  movi v7.16b, 0
  aese v7.16b, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40517	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	200	160026	1	160000	100
160204	40115	80109	101	80008	100	80012	0	300	0	320056	80113	200	0	80013	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	200	160026	1	160000	100
160204	40115	80109	101	80008	100	80012	0	300	0	320056	80113	200	0	80013	200	160026	1	160000	100
160204	40511	80242	103	80139	102	80143	0	300	0	320056	80113	200	0	80013	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	0	300	0	320316	80178	200	0	80078	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	0	300	0	320320	80179	200	0	80079	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	0	300	0	320188	80146	200	0	80046	200	160026	1	160000	100
160204	40091	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	200	160092	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5056

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	44118	80019	11	80008	10	80012	30	320000	80010	20	80000	20	160000	1	160000	10
160024	41294	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40451	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40429	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40449	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160060	1	160000	10
160024	40531	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40453	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40433	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40433	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40451	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  aese v0.16b, v16.16b
  aese v1.16b, v16.16b
  aese v2.16b, v16.16b
  aese v3.16b, v16.16b
  aese v4.16b, v16.16b
  aese v5.16b, v16.16b
  aese v6.16b, v16.16b
  aese v7.16b, v16.16b
  aese v8.16b, v16.16b
  aese v9.16b, v16.16b
  aese v10.16b, v16.16b
  aese v11.16b, v16.16b
  aese v12.16b, v16.16b
  aese v13.16b, v16.16b
  aese v14.16b, v16.16b
  aese v15.16b, v16.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80060	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160207	80202	160288	101	160187	100	160192	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100
160204	80040	160107	101	160006	100	160010	300	640044	160110	200	160015	200	320030	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80348	160017	11	160006	0	10	160010	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80061	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320122	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640288	160081	20	160076	20	0	320122	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10

AESE

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations