Icestorm: AESE + AESMC measurements

Code:

  aese v0.16b, v1.16b
  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
2004	3037	1003	1	1002	1002	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000
2004	3033	1001	1	1000	1000	75905	1000	2000	3000	1	2000

Test 2: Latency 1->1

Code:

  aese v0.16b, v1.16b
  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	30037	10103	101	10002	100	10002	0	300	0	768905	10100	200	0	20006	200	30006	1	20000	100
20205	30066	10107	101	10006	100	10032	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20205	30068	10108	101	10007	100	10033	0	300	0	768905	10100	200	0	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	0	300	0	769247	10132	200	0	20048	200	30006	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	30037	10013	11	10002	10	10002	30	768905	10010	20	20006	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20025	30066	10017	11	10006	10	10032	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10

Test 3: Latency 1->2

Code:

  aese v0.16b, v0.16b
  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30069	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100
20204	30033	10101	101	10000	100	10000	300	768905	10100	200	20004	200	30006	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30072	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10
20024	30033	10011	11	10000	10	10000	30	768905	10010	20	20000	20	30000	1	20000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  aese v0.16b, v8.16b
  aesmc v0.16b, v0.16b
  movi v1.16b, 0
  aese v1.16b, v8.16b
  aesmc v1.16b, v1.16b
  movi v2.16b, 0
  aese v2.16b, v8.16b
  aesmc v2.16b, v2.16b
  movi v3.16b, 0
  aese v3.16b, v8.16b
  aesmc v3.16b, v3.16b
  movi v4.16b, 0
  aese v4.16b, v8.16b
  aesmc v4.16b, v4.16b
  movi v5.16b, 0
  aese v5.16b, v8.16b
  aesmc v5.16b, v5.16b
  movi v6.16b, 0
  aese v6.16b, v8.16b
  aesmc v6.16b, v6.16b
  movi v7.16b, 0
  aese v7.16b, v8.16b
  aesmc v7.16b, v7.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240204	80457	80131	101	80030	100	80032	300	320030	80107	200	160012	200	240018	1	240000	100
240204	80056	80107	101	80006	100	80008	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240205	80071	80134	101	80033	100	80047	300	320030	80107	200	160012	200	240018	1	240000	100
240204	80041	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100
240204	80036	80105	101	80004	100	80006	300	320026	80106	200	160012	200	240018	1	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0230

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240024	84010	80276	11	80265	0	10	80267	30	320809	80210	20	160012	20	240000	1	240000	10
240024	82716	80201	11	80190	0	10	80190	30	320526	80140	20	160000	20	240000	1	240000	10
240024	81780	80139	11	80128	0	10	80128	30	320508	80136	20	160000	20	240000	1	240000	10
240025	82545	80210	11	80199	0	10	80216	30	320509	80134	20	160000	20	240000	1	240000	10
240024	83174	80235	11	80224	0	10	80224	30	320553	80146	20	160000	20	240000	1	240000	10
240024	81778	80137	11	80126	0	10	80126	30	320492	80132	20	160000	20	240000	1	240000	10
240024	82676	80184	11	80173	0	10	80173	30	320524	80140	20	160000	20	240000	1	240000	10
240024	81843	80134	11	80123	0	10	80123	30	320514	80137	20	160000	20	240000	1	240000	10
240024	81839	80140	11	80129	0	10	80129	30	320497	80133	20	160000	20	240000	1	240000	10
240024	81833	80136	11	80125	0	10	80125	30	320500	80134	20	160000	20	240000	1	240000	10

Test 5: throughput

Count: 16

Code:

  aese v0.16b, v16.16b
  aesmc v0.16b, v0.16b
  aese v1.16b, v16.16b
  aesmc v1.16b, v1.16b
  aese v2.16b, v16.16b
  aesmc v2.16b, v2.16b
  aese v3.16b, v16.16b
  aesmc v3.16b, v3.16b
  aese v4.16b, v16.16b
  aesmc v4.16b, v4.16b
  aese v5.16b, v16.16b
  aesmc v5.16b, v5.16b
  aese v6.16b, v16.16b
  aesmc v6.16b, v6.16b
  aese v7.16b, v16.16b
  aesmc v7.16b, v7.16b
  aese v8.16b, v16.16b
  aesmc v8.16b, v8.16b
  aese v9.16b, v16.16b
  aesmc v9.16b, v9.16b
  aese v10.16b, v16.16b
  aesmc v10.16b, v10.16b
  aese v11.16b, v16.16b
  aesmc v11.16b, v11.16b
  aese v12.16b, v16.16b
  aesmc v12.16b, v12.16b
  aese v13.16b, v16.16b
  aesmc v13.16b, v13.16b
  aese v14.16b, v16.16b
  aesmc v14.16b, v14.16b
  aese v15.16b, v16.16b
  aesmc v15.16b, v15.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
320204	80921	160110	101	160009	100	160013	300	640052	160112	200	320024	200	480039	1	320000	100
320204	80121	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480039	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640056	160113	200	320026	200	480036	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480036	1	320000	100
320204	80089	160109	101	160008	100	160012	300	640052	160112	200	320024	200	480036	1	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5425

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
320024	87760	160020	11	160009	10	160013	30	640052	160022	20	320024	20	480036	1	320000	10
320024	87412	160019	11	160008	10	160012	30	640000	160010	20	320000	20	480000	1	320000	10
320025	87262	160065	11	160054	10	160061	30	640373	160084	20	320092	20	480000	1	320000	10
320024	86802	160011	11	160000	10	160000	30	640000	160010	20	320000	20	480000	1	320000	10
320024	86884	160011	11	160000	10	160000	30	640000	160010	20	320000	20	480000	1	320000	10
320024	86900	160011	11	160000	10	160000	30	640000	160010	20	320000	20	480000	1	320000	10
320024	86919	160011	11	160000	10	160000	30	640000	160010	20	320000	20	480000	1	320000	10
320024	87248	160011	11	160000	10	160000	30	640000	160010	20	320000	20	480000	1	320000	10
320024	86811	160011	11	160000	10	160000	30	640369	160083	20	320090	20	480000	1	320000	10
320024	86812	160011	11	160000	10	160000	30	640000	160010	20	320000	20	480000	1	320000	10

AESE + AESMC

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations