Icestorm: BIC (vector, immediate, 2S) measurements

Code:

  bic v0.2s, #1

Initialization

  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000

Test 2: Latency 1->1

Code:

  bic v0.2s, #1

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	202	0	10046	2	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10006	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	10004	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  bic v0.2s, #1
  movi v1.16b, 0
  bic v1.2s, #1
  movi v2.16b, 0
  bic v2.2s, #1
  movi v3.16b, 0
  bic v3.2s, #1
  movi v4.16b, 0
  bic v4.2s, #1
  movi v5.16b, 0
  bic v5.2s, #1
  movi v6.16b, 0
  bic v6.2s, #1
  movi v7.16b, 0
  bic v7.2s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40504	80109	101	80008	100	80012	300	320056	80113	200	80013	200	80013	1	160000	100
160204	40117	80110	101	80009	100	80013	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40107	80110	101	80009	100	80013	300	320188	80146	200	80046	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80048	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160205	40132	80144	101	80043	100	80049	300	320052	80112	200	80012	200	80012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160025	43992	80055	11	80044	0	10	80050	30	320056	80023	20	80013	20	80000	1	160000	10
160024	41204	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40393	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40418	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40418	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40359	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40416	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40425	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40423	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40386	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10

Test 4: throughput

Count: 16

Code:

  bic v0.2s, #1
  bic v1.2s, #1
  bic v2.2s, #1
  bic v3.2s, #1
  bic v4.2s, #1
  bic v5.2s, #1
  bic v6.2s, #1
  bic v7.2s, #1
  bic v8.2s, #1
  bic v9.2s, #1
  bic v10.2s, #1
  bic v11.2s, #1
  bic v12.2s, #1
  bic v13.2s, #1
  bic v14.2s, #1
  bic v15.2s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80073	160105	101	160004	0	100	160008	300	640044	160110	200	160014	200	0	160015	1	0	160000	100
160204	80035	160109	101	160008	0	100	160012	300	640200	160152	200	160060	200	0	160015	1	0	160000	100
160204	80044	160107	101	160006	0	100	160010	300	640036	160108	200	160012	200	0	160012	1	0	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	160012	1	0	160000	100
160204	80035	160109	101	160008	0	100	160012	300	640036	160108	200	160012	200	0	160012	1	0	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	160012	1	0	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	160012	1	0	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	160012	1	0	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640364	160196	200	160108	200	0	160012	1	0	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	160012	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80195	160017	11	160006	10	160010	30	640044	160020	20	160014	20	160000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160063	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10

BIC (vector, immediate, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations