Icestorm: BIC (vector, immediate, 4S) measurements

Code:

  bic v0.4s, #1

Initialization

  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000

Test 2: Latency 1->1

Code:

  bic v0.4s, #1

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	307	509580	10136	202	10046	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	66	510844	10128	20	10125	20	10004	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10083	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  bic v0.4s, #1
  movi v1.16b, 0
  bic v1.4s, #1
  movi v2.16b, 0
  bic v2.4s, #1
  movi v3.16b, 0
  bic v3.4s, #1
  movi v4.16b, 0
  bic v4.4s, #1
  movi v5.16b, 0
  bic v5.4s, #1
  movi v6.16b, 0
  bic v6.4s, #1
  movi v7.16b, 0
  bic v7.4s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40509	80109	101	80008	100	80012	300	320056	80113	200	80013	200	80013	1	160000	100
160204	40111	80110	101	80009	100	80013	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	80012	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320204	80150	200	80050	200	80047	1	160000	100
160204	40428	80110	101	80009	100	80013	300	320200	80149	200	80049	200	80013	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	80012	1	160000	100
160205	40121	80145	101	80044	100	80048	300	320052	80112	200	80012	200	80012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43846	80019	11	80008	10	80012	30	320000	80010	20	80000	20	80000	1	160000	10
160024	41213	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40455	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40398	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40419	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40430	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	41520	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160025	40611	80054	11	80043	10	80049	30	320116	80039	20	80029	20	80000	1	160000	10
160024	40460	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10
160024	40419	80011	11	80000	10	80000	30	320000	80010	20	80000	20	80000	1	160000	10

Test 4: throughput

Count: 16

Code:

  bic v0.4s, #1
  bic v1.4s, #1
  bic v2.4s, #1
  bic v3.4s, #1
  bic v4.4s, #1
  bic v5.4s, #1
  bic v6.4s, #1
  bic v7.4s, #1
  bic v8.4s, #1
  bic v9.4s, #1
  bic v10.4s, #1
  bic v11.4s, #1
  bic v12.4s, #1
  bic v13.4s, #1
  bic v14.4s, #1
  bic v15.4s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80091	160105	101	160004	100	160008	0	300	0	640044	160110	200	0	160014	200	160015	1	160000	100
160205	80079	160141	101	160040	100	160052	2883	166308	46091	578407	151368	6737	3477	143552	200	160106	1	160000	100
160204	80035	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	160014	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	160012	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	160012	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	160012	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	160012	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	160012	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	160012	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80237	160015	11	160004	10	160008	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80076	160011	11	160000	10	160000	30	640772	160203	20	160193	20	160000	1	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160025	80071	160052	11	160041	10	160053	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	160000	1	160000	10

BIC (vector, immediate, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations