Icestorm: BIF (vector, 8B) measurements

Code:

  bif v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  bif v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	307	509780	10138	202	10050	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	314	511376	10248	204	10172	206	30510	4	10000	100
10204	20240	10152	104	10048	103	10144	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509246	10020	20	10004	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  bif v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	30018	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10205	20066	10109	101	10008	102	10034	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10025	20066	10029	21	10008	20	10034	70	509248	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  bif v0.8b, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	30018	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30138	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10006	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bif v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  bif v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  bif v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  bif v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  bif v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  bif v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  bif v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  bif v7.8b, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40499	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40112	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320200	80149	200	80049	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	43832	80020	11	80009	10	80013	30	320056	80023	20	80013	20	0	240000	1	0	160000	10
160024	41182	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40394	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40421	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40394	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40970	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40390	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240000	1	0	160000	10
160024	40432	80011	11	80000	10	80000	30	320000	80010	20	80000	20	0	240141	1	0	160000	10

Test 6: throughput

Count: 16

Code:

  bif v0.8b, v16.8b, v17.8b
  bif v1.8b, v16.8b, v17.8b
  bif v2.8b, v16.8b, v17.8b
  bif v3.8b, v16.8b, v17.8b
  bif v4.8b, v16.8b, v17.8b
  bif v5.8b, v16.8b, v17.8b
  bif v6.8b, v16.8b, v17.8b
  bif v7.8b, v16.8b, v17.8b
  bif v8.8b, v16.8b, v17.8b
  bif v9.8b, v16.8b, v17.8b
  bif v10.8b, v16.8b, v17.8b
  bif v11.8b, v16.8b, v17.8b
  bif v12.8b, v16.8b, v17.8b
  bif v13.8b, v16.8b, v17.8b
  bif v14.8b, v16.8b, v17.8b
  bif v15.8b, v16.8b, v17.8b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80063	160106	101	160005	100	160009	300	640044	160110	200	160014	200	480042	1	160000	100
160205	80079	160143	101	160042	100	160054	300	640044	160110	200	160014	200	480042	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640208	160154	200	160064	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80219	160015	11	160004	10	160008	30	640040	160019	20	160013	20	480183	1	160000	10
160024	80077	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480180	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10

BIF (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations