Icestorm: BIT (vector, 8B) measurements

Code:

  bit v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  bit v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509246	10020	20	10004	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  bit v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	307	509580	10136	202	10044	24209	15732	30197	11188	7322	10033	13114
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	304	509580	10136	202	10050	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10006	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  bit v0.8b, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30018	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509580	10134	200	10048	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	30012	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bit v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  bit v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  bit v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  bit v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  bit v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  bit v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  bit v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  bit v7.8b, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40463	80110	101	80009	100	80013	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40121	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40107	80109	101	80008	100	80012	300	320204	80150	200	80050	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43864	80019	11	80008	10	80012	30	320056	80023	20	80013	20	240039	1	160000	10
160024	41324	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40397	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40431	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40429	80011	11	80000	10	80000	30	320056	80023	20	80013	20	240039	1	160000	10
160024	40425	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40391	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240039	1	160000	10
160024	40571	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40431	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  bit v0.8b, v16.8b, v17.8b
  bit v1.8b, v16.8b, v17.8b
  bit v2.8b, v16.8b, v17.8b
  bit v3.8b, v16.8b, v17.8b
  bit v4.8b, v16.8b, v17.8b
  bit v5.8b, v16.8b, v17.8b
  bit v6.8b, v16.8b, v17.8b
  bit v7.8b, v16.8b, v17.8b
  bit v8.8b, v16.8b, v17.8b
  bit v9.8b, v16.8b, v17.8b
  bit v10.8b, v16.8b, v17.8b
  bit v11.8b, v16.8b, v17.8b
  bit v12.8b, v16.8b, v17.8b
  bit v13.8b, v16.8b, v17.8b
  bit v14.8b, v16.8b, v17.8b
  bit v15.8b, v16.8b, v17.8b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160205	80116	160139	101	160038	100	160050	300	640044	160110	200	160013	200	480039	1	160000	100
160204	80044	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480042	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160107	101	160006	100	160010	300	640044	160110	200	160013	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160205	80068	160141	101	160040	100	160052	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80168	160017	11	160006	0	10	160010	30	640044	160020	20	160014	20	480000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480135	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480189	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480183	1	160000	10
160024	80034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10

BIT (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations