Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BSL (vector, 8B)

Test 1: uops

Code:

  bsl v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000

Test 2: Latency 1->1

Code:

  bsl v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030129111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010

Test 3: Latency 1->2

Code:

  bsl v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204200331010110110000010010000300509248101002001000620030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10205200661011110310008010210034300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100002030000111000010
10025200661002921100082010034705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010

Test 4: Latency 1->3

Code:

  bsl v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bsl v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  bsl v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  bsl v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  bsl v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  bsl v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  bsl v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  bsl v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  bsl v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160204404648010910180008100800123003200568011320080013200024003610160000100
160204401088011010180009100800133003200568011320080013200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123073201848014720280045200024003610160000100
160204400968010910180008100800123003200568011320080013200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244380780020118000910800133032000080010208000020240000116000010
1600244133380011118000010800003032018880056208004620240000116000010
1600244044380011118000010800003032000080010208000020240000116000010
1600244043580011118000010800003032000080010208000020240000116000010
1600244043380011118000010800003032000080010208000020240000116000010
1600244041680011118000010800003032000080010208000020240000116000010
1600244042780011118000010800003032000080010208000020240000116000010
1600244042780011118000010800003032000080010208000020240000116000010
1600244041680011118000010800003032000080010208000020240000116000010
1600244042080011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  bsl v0.8b, v16.8b, v17.8b
  bsl v1.8b, v16.8b, v17.8b
  bsl v2.8b, v16.8b, v17.8b
  bsl v3.8b, v16.8b, v17.8b
  bsl v4.8b, v16.8b, v17.8b
  bsl v5.8b, v16.8b, v17.8b
  bsl v6.8b, v16.8b, v17.8b
  bsl v7.8b, v16.8b, v17.8b
  bsl v8.8b, v16.8b, v17.8b
  bsl v9.8b, v16.8b, v17.8b
  bsl v10.8b, v16.8b, v17.8b
  bsl v11.8b, v16.8b, v17.8b
  bsl v12.8b, v16.8b, v17.8b
  bsl v13.8b, v16.8b, v17.8b
  bsl v14.8b, v16.8b, v17.8b
  bsl v15.8b, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801321601071011600061001600103006400441601102001600142004800391160000100
160204800341601071011600061001600103006400361601082001600122004801921160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006402081601542001600642004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004801801160000100
160204800341601051011600041001600083006400441601102001600142004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248016216001811160007010160011306400001600102016000020480000116000010
1600248003416001111160000010160000306400001600102016000020480000116000010
1600248003416001111160000010160000306400001600102016000020480000116000010
1600248003416001111160000010160000306400001600102016000020480000116000010
1600248003416001111160000010160000306400001600102016000020480000116000010
1600258006916005311160042010160054306400001600102016000020480000116000010
1600248003416001111160000010160000306400001600102016000020480000116000010
1600248003416001111160000010160000306400001600102016000020480000116000010
1600248003416001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010