Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGE (zero, 8B)

Test 1: uops

Code:

  cmge v0.8b, v0.8b, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000

Test 2: Latency 1->2

Code:

  cmge v0.8b, v0.8b, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620010006110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020520066101091011000810010034300509248101002001000620010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100062010004111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000655095801005420100432010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  cmge v0.8b, v8.8b, #0
  cmge v1.8b, v8.8b, #0
  cmge v2.8b, v8.8b, #0
  cmge v3.8b, v8.8b, #0
  cmge v4.8b, v8.8b, #0
  cmge v5.8b, v8.8b, #0
  cmge v6.8b, v8.8b, #0
  cmge v7.8b, v8.8b, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020440045801071018000610080010300320036801082008001220080014180000100
8020440044801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
80024402258002921800080208001270320044800302080016200800001108000010
80024400348002121800000208000070320208800742080066200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010
80024400348002121800000208000070320000800202080000200800001108000010