Icestorm: CMHI (register, 8B) measurements

Code:

  cmhi v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50580	1034	1041	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  cmhi v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10006	200	20012	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  cmhi v0.8b, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	307	510312	10174	202	10086	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10005	200	20012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  cmhi v0.8b, v8.8b, v9.8b
  cmhi v1.8b, v8.8b, v9.8b
  cmhi v2.8b, v8.8b, v9.8b
  cmhi v3.8b, v8.8b, v9.8b
  cmhi v4.8b, v8.8b, v9.8b
  cmhi v5.8b, v8.8b, v9.8b
  cmhi v6.8b, v8.8b, v9.8b
  cmhi v7.8b, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40087	80107	101	80006	0	100	80010	300	320044	80110	200	80014	200	160026	1	80000	100
80204	40034	80107	101	80006	0	100	80010	300	320044	80110	200	80014	200	160024	1	80000	100
89428	69268	88868	5857	80047	2964	5684	80063	300	320044	80110	200	80014	200	160026	1	80000	100
80205	40069	80143	103	80040	0	102	80052	300	320036	80108	200	80012	200	160026	1	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320044	80110	200	80014	200	160120	1	80000	100
80204	40044	80107	101	80006	0	100	80010	300	320036	80108	200	80012	200	160028	1	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40217	80019	11	80008	0	10	80012	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10
80024	40034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	80000	10

CMHI (register, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations