Icestorm: CMLE (zero, 2D) measurements

Code:

  cmle v0.2d, v0.2d, #0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1040	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  cmle v0.2d, v0.2d, #0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10006	200	10006	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10205	20066	10109	101	10008	0	100	10034	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509580	10054	20	10048	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  cmle v0.2d, v8.2d, #0
  cmle v1.2d, v8.2d, #0
  cmle v2.2d, v8.2d, #0
  cmle v3.2d, v8.2d, #0
  cmle v4.2d, v8.2d, #0
  cmle v5.2d, v8.2d, #0
  cmle v6.2d, v8.2d, #0
  cmle v7.2d, v8.2d, #0

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80205	40068	80141	101	80040	100	80052	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40388	80295	101	80194	100	80198	300	320036	80108	200	80012	200	80201	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80205	40069	80143	101	80042	100	80054	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40177	80027	21	80006	0	20	80010	70	320044	80030	20	80016	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	80067	11	80000	10

CMLE (zero, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations