Icestorm: DUP (general, 2D) measurements

Code:

  dup v0.2d, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	613	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	536	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	536	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	536	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	536	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	536	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	536	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	536	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.2d, x0
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 9.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	90030	40101	10101	20000	10000	100	20000	10001	300	1376312	2318460	30101	200	10002	20004	200	10002	20002	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	90031	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	202	10021	20040	10003	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376344	2318486	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	90030	40101	10101	20000	10000	100	20000	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30205	90063	40110	10105	20003	10002	102	20029	10000	300	1376328	2318460	30100	200	10002	20002	200	10002	20004	10001	10000	10000	10100
30204	90032	40101	10101	20000	10000	100	20000	10001	300	1376338	2318486	30101	200	10002	20004	200	10002	20002	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 9.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	90032	40011	10011	20000	10000	10	20000	10000	30	1376320	2318460	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376520	2318772	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30026	90101	40023	10013	20006	10004	10	20056	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1378231	2321502	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90036	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	90030	40011	10011	20000	10000	10	20000	10000	30	1376328	2318460	30010	20	10000	20000	20	10022	20042	10003	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  dup v0.2d, x8
  dup v1.2d, x8
  dup v2.2d, x8
  dup v3.2d, x8
  dup v4.2d, x8
  dup v5.2d, x8
  dup v6.2d, x8
  dup v7.2d, x8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40154	160117	101	80007	80009	100	80013	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40093	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	271750	678614	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40448	160115	101	80006	80008	100	80012	80012	300	255279	658857	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40094	160115	101	80006	80008	100	80012	80012	300	251830	656064	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	40656	160019	11	80002	80006	10	80013	80000	30	347895	767970	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40117	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40041	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

DUP (general, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations