Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DUP (general, 4S)

Test 1: uops

Code:

  dup v0.4s, w0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
20046002001110001000100010003000800020001000100010001000110001000
20045372001110001000100010003000800020001000100010001000110001000
20045392001110001000100010003000800020001000100010001000110001000
20045362001110001000100010003000800020001000100010001000110001000
20045362001110001000100010003000800020001000100010001000110001000
20045362001110001000100010003000800020001000100010001000110001000
20045362001110001000100010003000800020001000100010001000110001000
20045362001110001000100010003000800020001000100010001000110001000
20045362001110001000100010003000800020001000100010001000110001000
20045362001110001000100010003000800020001000100010001000110001000

Test 2: Latency 1->2 roundtrip

Code:

  dup v0.4s, w0
  fmov x0, d0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 9.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
302049003040101101012000010000100200001000130013763282318460301012001000220004200100022000410001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000410001100001000010100
302049003040101101012000010000100200001001730013775942320503301462001002120039200100022000210001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000210001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000210001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000210001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000210001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000210001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000210001100001000010100
302049003040101101012000010000100200001000030013763282318460301002001000220002200100022000210001100001000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 9.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
30024900354001110011200001000010200001000130137632823184603001120100022000420100022000410001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100002000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100002000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100002000010001100001000010010
30024900304001110011200001000010200001001830137649823187383005620100212003920100002000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100002000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100002000010001100001000010010
30024900404001110011200001000010200001000030137637623185383001020100002000020100002000010001100001000010010
30024900304001110011200001000010200001000030137632823184603001020100002000020100222004210003100001000010010
30024900324001110011200001000010200001000030137640823185903001020100002000020100002000010001100001000010010

Test 3: throughput

Count: 8

Code:

  dup v0.4s, w8
  dup v1.4s, w8
  dup v2.4s, w8
  dup v3.4s, w8
  dup v4.4s, w8
  dup v5.4s, w8
  dup v6.4s, w8
  dup v7.4s, w8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020440176160115101800068000810080012800123002410486418731601242008001280012200800128001218000080000100
16020440093160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440096160115101800068000810080012800123002413306421461601242008001280012200800128001218000080000100
16020440093160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800548005418000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002440442160027118000780009108001380012302400366400801600342080012800122080000800001800008000010
16002440083160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440058160011118000080000108000080055303059427139151601202080055800552080000800001800008000010