Icestorm: FCCMPE (scalar, D) measurements

Code:

  fccmpe d0, d1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fccmpe d0, d1, #0, lt
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	60138	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60144	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	30	1019580	20044	20	20048	20	60018	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fccmpe d0, d1, #0, lt
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20006	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60144	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	10000	10

Test 4: Latency 3->3

Code:

  fccmpe d0, d1, #0, lt

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
10204	20033	10201	201	10000	200	10000	700	249768	10200	200	10006	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100
10204	20033	10201	201	10000	200	10000	700	249769	10200	200	10004	200	30012	101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249768	10020	20	10000	20	30000	11	10
10025	20066	10029	21	10008	20	10021	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmpe d0, d1, #0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0736

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
160204	85889	160107	80105	80002	0	80106	80005	240321	556622	160114	80207	80007	200	240021	80008	100
160204	85886	160107	80105	80002	0	80106	80005	240321	509638	160114	80207	80007	200	240018	80005	100
160204	85886	160107	80105	80002	0	80106	80005	240318	560031	160111	80206	80006	200	240018	80005	100
160204	85886	160107	80105	80002	0	80106	80005	240318	560031	160111	80206	80006	200	240018	80005	100
160204	85886	160107	80105	80002	0	80106	80005	240318	560031	160111	80206	80006	200	240018	80005	100
160204	85886	160107	80105	80002	0	80106	80005	240318	560031	160111	80206	80006	200	240018	80005	100
160205	85923	160143	80125	80018	0	80126	80025	240321	476517	160113	80207	80006	200	240018	80005	100
160204	85886	160107	80105	80002	0	80106	80005	240318	560031	160111	80206	80006	200	240018	80005	100
160204	85886	160107	80105	80002	0	80106	80005	240318	560031	160111	80206	80006	200	240018	80005	100
160204	85886	160107	80105	80002	0	80106	80005	240318	560031	160111	80206	80006	200	240018	80005	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0482

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	83934	160019	80016	80003	80017	80005	240045	551719	160020	80025	80005	20	0	240000	80001	0	0	10
160024	85620	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240000	80001	0	0	10
160024	83856	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240000	80001	0	0	10
160024	83856	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240000	80001	0	0	10
160024	83858	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240000	80001	0	0	10
160024	83856	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240072	80024	0	0	10
160024	83856	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240000	80001	0	0	10
160024	83856	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240000	80001	0	0	10
160024	83856	160011	80011	80000	80010	80000	240030	476429	160010	80020	80000	20	0	240000	80001	0	0	10
160024	83856	160011	80011	80000	80010	80000	240087	535204	160048	80039	80019	20	0	240000	80001	0	0	10

FCCMPE (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations