Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCCMP (scalar, D)

Test 1: uops

Code:

  fccmp d0, d1, #0, lt
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001
100420331001110001000247691000100030001

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fccmp d0, d1, #0, lt
  fcsel d0, d2, d3, eq
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20204400332010110120000100200003001019248201002002000620060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20025400662001911200081020034301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20025400662001911200081020034301019248200102020000206000011000010
20025400662001911200081020034301019248200102020000206001811000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fccmp d0, d1, #0, lt
  fcsel d1, d2, d3, eq
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20204400332010110120000100200003001019248201002002000620060018110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100
20204400332010110120000100200003001019580201342002004420060012110000100
20204400332010110120000100200003001019248201002002000420060012110000100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206014411000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010
20024400332001111200001020000301019248200102020000206000011000010

Test 4: Latency 3->3

Code:

  fccmp d0, d1, #0, lt
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
102042003310201201100002001000070024976810200200100062000300121010100
102042003310201201100002001000070024976910200200100042000300181010100
102042003310201201100002001000070024976810200200100062000300121010100
102042003310201201100002001000070024976910200200100042000300121010100
102042003310201201100002001000070024976910200200100042000300121010100
102042003310201201100002001000070024976910200200100042000300121010100
102042003310201201100002001000070024976910200200100042000300121010100
102042003310201201100002001000070024976910200200100042000300121010100
102042003310201201100002001000070024976910200200100042000300121010100
102042003310201201100002001000070024976910200200100042000300121010100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
100242003310021211000020100007024976810020201000620300001110
100242003310021211000020100007024976910020201000020300001110
100242003310021211000020100007024976910020201000020300001110
100242003310021211000020100007024976910020201000020300001110
100242003310021211000020100007024976910020201000020300001110
100242003310021211000020100006724990710041201003220300001110
100242003310021211000020100007024976910020201000020300001110
100242003310021211000020100007024976910020201000020300001110
100242003310021211000020100007024976910020201000020300001110
100242003310021211000020100007024976910020201000020300001110

Test 5: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  ands xzr, xzr, xzr
  fccmp d0, d1, #0, lt
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0736

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
16020485910160107801058000208010680005240321560037160114802078000720024002180008100
16020483941160111801088000308010780006240321560045160114802078000720024001880005100
16020485886160107801058000208010680005240318560031160111802068000620024001880005100
16020485886160107801058000208010680005240318560031160111802068000620024001880005100
16020485886160107801058000208010680005240318560031160111802068000620024013880047100
16020485896160107801058000208010680005240321476896160113802078000620024001880005100
16020485886160107801058000208010680005240318560031160111802068000620024001880005100
16020485886160107801058000208010680005240318560031160111802068000620024001880005100
16020485886160107801058000208010680005240318560031160111802068000620024001880005100
16020485886160107801058000208010680005240318560031160111802068000620024001880005100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0482

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
16002485727160017800158000280016800052400305516971600108002080000202400008000110
16002485573160011800118000080010800002400304769211600108002080000202400008000110
16002483856160011800118000080010800002400304764171600108002080000202400008000110
16002483856160011800118000080010800002400304764171600108002080000202400008000110
16002483856160011800118000080010800002400304764171600108002080000202400008000110
16002483856160011800118000080010800002400304764171600108002080000202400758002510
16002483871160011800118000080010800002400304764171600108002080000202400008000110
16002483861160011800118000080010800002400304764171600108002080000202400008000110
16002483856160011800118000080010800002400304764171600108002080000202400008000110
16002483856160011800118000080010800002400304764171600108002080000202400008000110