Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMGT (scalar, H)

Test 1: uops

Code:

  fcmgt h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000

Test 2: Latency 1->2

Code:

  fcmgt h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020088110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020520066101091011000810010034300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020010111000010
10025200661002921100082010034705092471002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10025200661002921100082010034705092481002020100002020000111000010

Test 3: Latency 1->3

Code:

  fcmgt h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620020012110000100
1020420033101011011000010010000300509248101002001000620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420220092210000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020098111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020094111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  fcmgt h0, h8, h9
  fcmgt h1, h8, h9
  fcmgt h2, h8, h9
  fcmgt h3, h8, h9
  fcmgt h4, h8, h9
  fcmgt h5, h8, h9
  fcmgt h6, h8, h9
  fcmgt h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204401038010510180004100800080300032004480110200080014200160028180000100
80204401068015410180053100800570300032003680108200080012200160024180000100
80204400348010510180004100800080300032003680108200080012200160024180000100
80204400348010510180004100800080300032019280150200080060200160024180000100
80204400348010510180004100800080300032003680108200080012200160024180000100
80204400348010510180004100800080300032003680108200080012200160024180000100
80204400348010510180004100800080300032003680108200080012200160024180000100
80204400348010510180004100800080300032003680108200080012200160024180000100
80204400348010710180006100800100300032003680108200080012200160024180000100
80204400348010510180004100800080300032003680108200080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244022280029218000820800126832000080020208000020160000118000010
800244003480021218000020800006532000080020208000020160000118000010
800244003480021218000020800006532000080020208000020160000118000010
800244003480021218000020800006532000080020208000020160120118000010
800244003480021218000020800006532000080020208000020160000118000010
800244003480021218000020800006532000080020208000020160126118000010
800244003480021218000020800006532000080020208000020160000118000010
800244003480021218000020800006532000080020208000020160000118000010
800244003480021218000020800006532000080020208000020160000118000010
800244003480021218000020800006532000080020208000020160000118000010