Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMLA (vector, 2D)

Test 1: uops

Code:

  fcmla v0.2d, v1.2d, v2.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->1

Code:

  fcmla v0.2d, v1.2d, v2.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028904101302001004420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 3: Latency 1->2

Code:

  fcmla v0.2d, v0.2d, v1.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100042030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030132111000010

Test 4: Latency 1->3

Code:

  fcmla v0.2d, v1.2d, v0.2d, #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10205400661010510110004100100303001028904101302001004320030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.2d, v8.2d, v9.2d, #90
  movi v1.16b, 0
  fcmla v1.2d, v8.2d, v9.2d, #90
  movi v2.16b, 0
  fcmla v2.2d, v8.2d, v9.2d, #90
  movi v3.16b, 0
  fcmla v3.2d, v8.2d, v9.2d, #90
  movi v4.16b, 0
  fcmla v4.2d, v8.2d, v9.2d, #90
  movi v5.16b, 0
  fcmla v5.2d, v8.2d, v9.2d, #90
  movi v6.16b, 0
  fcmla v6.2d, v8.2d, v9.2d, #90
  movi v7.16b, 0
  fcmla v7.2d, v8.2d, v9.2d, #90
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044054180110101800091008001303000320056801132000800132002400391160000100
1602044012180110101800091008001303000320056801132000800132002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044009880109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002401381160000100
1602044009880109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602054014480147101800461008005003000320052801122000800122002400391160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244383080011118000010800003032000080010208000020240000116000010
1600244129780011118000010800003032000080010208000020240000116000010
1600244042580011118000010800003032000080010208000020240000116000010
1600244168480011118000010800003032000080010208000020240000116000010
1600244041280011118000010800003032000080010208000020240144116000010
1600244050380011118000010800003032000080010208000020240000116000010
1600244041580011118000010800003032000080010208000020240000116000010
1600244040680011118000010800003032000080010208000020240000116000010
1600244042480011118000010800003032000080010208000020240000116000010
1600244040680011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  fcmla v0.2d, v16.2d, v17.2d, #90
  fcmla v1.2d, v16.2d, v17.2d, #90
  fcmla v2.2d, v16.2d, v17.2d, #90
  fcmla v3.2d, v16.2d, v17.2d, #90
  fcmla v4.2d, v16.2d, v17.2d, #90
  fcmla v5.2d, v16.2d, v17.2d, #90
  fcmla v6.2d, v16.2d, v17.2d, #90
  fcmla v7.2d, v16.2d, v17.2d, #90
  fcmla v8.2d, v16.2d, v17.2d, #90
  fcmla v9.2d, v16.2d, v17.2d, #90
  fcmla v10.2d, v16.2d, v17.2d, #90
  fcmla v11.2d, v16.2d, v17.2d, #90
  fcmla v12.2d, v16.2d, v17.2d, #90
  fcmla v13.2d, v16.2d, v17.2d, #90
  fcmla v14.2d, v16.2d, v17.2d, #90
  fcmla v15.2d, v16.2d, v17.2d, #90
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800691601051011600041001600080300064004416011020001600142004800421160000100
160204800361601071011600061001600100300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004801891160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064038416020120001601172004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100
160204800361601051011600041001600080300064003616010820001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024802201600161116000510160009030064021616006620016006620480192116000010
160024800621600111116000010160000030064000016001020016000020480000116000010
160024800361600111116000010160000030064000016001020016000020480000116000010
160024800361600111116000010160000030064000016001020016000020480000116000010
160024800361600111116000010160000030064000016001020016000020480000116000010
160024800391600111116000010160000030064000016001020016000020480000116000010
160024800361600111116000010160000030064000016001020016000020480000116000010
160024800361600111116000010160000030064022016006720016006420480000116000010
160024800361600111116000010160000030064000016001020016000020480000116000010
160024800361600111116000010160000030064000016001020016000020480000116000010