Icestorm: FCMLA (vector, 2S) measurements

Code:

  fcmla v0.2s, v1.2s, v2.2s, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fcmla v0.2s, v1.2s, v2.2s, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  fcmla v0.2s, v0.2s, v1.2s, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028904	10050	20	10046	20	0	30474	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	906	714	30132	413	376	10003	564
10024	40084	10027	21	10006	20	10031	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	70	1029657	10082	20	10076	20	0	30000	11	0	10000	10
10024	40033	10021	21	10000	20	10000	67	1029657	10082	20	10077	20	0	30234	11	0	10000	10
10024	40186	10039	21	10018	20	10093	65	1030193	10113	20	10114	20	0	30231	11	0	10000	10

Test 4: Latency 1->3

Code:

  fcmla v0.2s, v1.2s, v0.2s, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028904	10130	200	10047	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	202	30132	2	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10205	40066	10105	101	10004	100	10030	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028904	10130	202	10043	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	307	1028904	10132	202	10046	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30135	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10006	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	0	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.2s, v8.2s, v9.2s, #90
  movi v1.16b, 0
  fcmla v1.2s, v8.2s, v9.2s, #90
  movi v2.16b, 0
  fcmla v2.2s, v8.2s, v9.2s, #90
  movi v3.16b, 0
  fcmla v3.2s, v8.2s, v9.2s, #90
  movi v4.16b, 0
  fcmla v4.2s, v8.2s, v9.2s, #90
  movi v5.16b, 0
  fcmla v5.2s, v8.2s, v9.2s, #90
  movi v6.16b, 0
  fcmla v6.2s, v8.2s, v9.2s, #90
  movi v7.16b, 0
  fcmla v7.2s, v8.2s, v9.2s, #90

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40484	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40108	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5051

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43823	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41247	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40410	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40437	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40430	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240147	1	160000	10
160024	40607	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40410	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40354	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40403	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  fcmla v0.2s, v16.2s, v17.2s, #90
  fcmla v1.2s, v16.2s, v17.2s, #90
  fcmla v2.2s, v16.2s, v17.2s, #90
  fcmla v3.2s, v16.2s, v17.2s, #90
  fcmla v4.2s, v16.2s, v17.2s, #90
  fcmla v5.2s, v16.2s, v17.2s, #90
  fcmla v6.2s, v16.2s, v17.2s, #90
  fcmla v7.2s, v16.2s, v17.2s, #90
  fcmla v8.2s, v16.2s, v17.2s, #90
  fcmla v9.2s, v16.2s, v17.2s, #90
  fcmla v10.2s, v16.2s, v17.2s, #90
  fcmla v11.2s, v16.2s, v17.2s, #90
  fcmla v12.2s, v16.2s, v17.2s, #90
  fcmla v13.2s, v16.2s, v17.2s, #90
  fcmla v14.2s, v16.2s, v17.2s, #90
  fcmla v15.2s, v16.2s, v17.2s, #90

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80076	160105	101	160004	100	160008	300	640044	160110	200	160014	200	480039	1	160000	100
160204	80036	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480042	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480039	1	160000	100
160204	80036	160107	101	160006	100	160010	300	640044	160110	200	160014	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80053	160017	11	160006	10	160010	0	30	0	640044	160020	20	0	160014	20	480000	1	160000	10
160024	80053	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480192	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10

FCMLA (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations