Icestorm: FCMLA (vector, 8H) measurements

Code:

  fcmla v0.8h, v1.8h, v2.8h, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  fcmla v0.8h, v1.8h, v2.8h, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	314	1029251	10164	204	10084	200	30132	1	10000	100
10205	40066	10105	101	10004	100	10030	300	1028557	10100	200	10004	200	30132	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	202	30138	2	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028890	10050	20	10041	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  fcmla v0.8h, v0.8h, v1.8h, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	202	30138	2	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	66	1028904	10050	20	10043	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  fcmla v0.8h, v1.8h, v0.8h, #90

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10006	200	30018	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10205	40066	10107	103	10004	102	10030	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	0	70	0	1028557	10020	20	0	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.8h, v8.8h, v9.8h, #90
  movi v1.16b, 0
  fcmla v1.8h, v8.8h, v9.8h, #90
  movi v2.16b, 0
  fcmla v2.8h, v8.8h, v9.8h, #90
  movi v3.16b, 0
  fcmla v3.8h, v8.8h, v9.8h, #90
  movi v4.16b, 0
  fcmla v4.8h, v8.8h, v9.8h, #90
  movi v5.16b, 0
  fcmla v5.8h, v8.8h, v9.8h, #90
  movi v6.16b, 0
  fcmla v6.8h, v8.8h, v9.8h, #90
  movi v7.16b, 0
  fcmla v7.8h, v8.8h, v9.8h, #90

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40465	80109	101	80008	100	80012	0	300	0	320056	80113	200	0	80013	200	240039	1	160000	100
160204	40110	80110	101	80009	100	80013	0	300	0	320052	80112	200	0	80012	200	240039	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320056	80113	200	0	80013	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100
160205	40123	80147	101	80046	100	80050	0	300	0	320052	80112	200	0	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	44106	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41324	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240423	1	160000	10
160024	40455	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40412	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40424	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  fcmla v0.8h, v16.8h, v17.8h, #90
  fcmla v1.8h, v16.8h, v17.8h, #90
  fcmla v2.8h, v16.8h, v17.8h, #90
  fcmla v3.8h, v16.8h, v17.8h, #90
  fcmla v4.8h, v16.8h, v17.8h, #90
  fcmla v5.8h, v16.8h, v17.8h, #90
  fcmla v6.8h, v16.8h, v17.8h, #90
  fcmla v7.8h, v16.8h, v17.8h, #90
  fcmla v8.8h, v16.8h, v17.8h, #90
  fcmla v9.8h, v16.8h, v17.8h, #90
  fcmla v10.8h, v16.8h, v17.8h, #90
  fcmla v11.8h, v16.8h, v17.8h, #90
  fcmla v12.8h, v16.8h, v17.8h, #90
  fcmla v13.8h, v16.8h, v17.8h, #90
  fcmla v14.8h, v16.8h, v17.8h, #90
  fcmla v15.8h, v16.8h, v17.8h, #90

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80055	160108	101	160007	100	160011	300	640044	160110	200	160014	200	480042	1	160000	100
160204	80036	160107	101	160006	100	160010	300	640044	160110	200	160013	200	480036	1	160000	100
160204	80039	160107	101	160006	100	160010	300	640044	160110	200	160013	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160206	80108	160181	101	160080	100	160100	300	640044	160110	200	160013	200	480036	1	160000	100
160204	80036	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80236	160015	11	160004	10	160008	30	640044	160020	20	160014	20	0	480042	1	0	160000	10
160024	80036	160017	11	160006	10	160010	30	640220	160067	20	160064	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	480201	1	0	160000	10
160024	80096	160015	11	160004	10	160008	30	640224	160068	20	160067	20	0	480000	1	0	160000	10
160024	80037	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	480000	1	0	160000	10

FCMLA (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations