Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMLA (vector, by element, 4H)

Test 1: uops

Code:

  fcmla v0.4h, v1.4h, v2.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000
100440331001110001000101557100010000030001010000

Test 2: Latency 1->1

Code:

  fcmla v0.4h, v1.4h, v2.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003071028823101322021004220030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028904101302001004420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
100244003310021211000002010000701028557100202010000200300001101000010
11300323231031350971162405448811189701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010
100244003310021211000002010000701028557100202010000200300001101000010

Test 3: Latency 1->2

Code:

  fcmla v0.4h, v0.4h, v1.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10205400661010510110004100100303001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030114111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 4: Latency 1->3

Code:

  fcmla v0.4h, v1.4h, v0.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100254006610025211000420100307010285571002020100042030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.4h, v8.4h, v9.h[1], #90
  movi v1.16b, 0
  fcmla v1.4h, v8.4h, v9.h[1], #90
  movi v2.16b, 0
  fcmla v2.4h, v8.4h, v9.h[1], #90
  movi v3.16b, 0
  fcmla v3.4h, v8.4h, v9.h[1], #90
  movi v4.16b, 0
  fcmla v4.4h, v8.4h, v9.h[1], #90
  movi v5.16b, 0
  fcmla v5.4h, v8.4h, v9.h[1], #90
  movi v6.16b, 0
  fcmla v6.4h, v8.4h, v9.h[1], #90
  movi v7.16b, 0
  fcmla v7.4h, v8.4h, v9.h[1], #90
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044049280109101800081008001230032005680113200800132002400391160000100
1602044011780110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002401441160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400391160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244405380019118000810800123032000080010208000020240000116000010
1600244425880020118000910800133032000080010208000020240000116000010
1600254062280054118004310800473032000080010208000020240000116000010
1600244041580011118000010800003032000080010208000020240000116000010
1600244039080011118000010800003032000080010208000020240000116000010
1600244043180011118000010800003032000080010208000020240000116000010
1600244042080011118000010800003032000080010208000020240000116000010
1600244042280011118000010800003032000080010208000020240000116000010
1600244042480011118000010800003032000080010208000020240000116000010
1600244040880011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  fcmla v0.4h, v16.4h, v17.h[1], #90
  fcmla v1.4h, v16.4h, v17.h[1], #90
  fcmla v2.4h, v16.4h, v17.h[1], #90
  fcmla v3.4h, v16.4h, v17.h[1], #90
  fcmla v4.4h, v16.4h, v17.h[1], #90
  fcmla v5.4h, v16.4h, v17.h[1], #90
  fcmla v6.4h, v16.4h, v17.h[1], #90
  fcmla v7.4h, v16.4h, v17.h[1], #90
  fcmla v8.4h, v16.4h, v17.h[1], #90
  fcmla v9.4h, v16.4h, v17.h[1], #90
  fcmla v10.4h, v16.4h, v17.h[1], #90
  fcmla v11.4h, v16.4h, v17.h[1], #90
  fcmla v12.4h, v16.4h, v17.h[1], #90
  fcmla v13.4h, v16.4h, v17.h[1], #90
  fcmla v14.4h, v16.4h, v17.h[1], #90
  fcmla v15.4h, v16.4h, v17.h[1], #90
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800931601051011600041001600083006400441601102001600132004800421160000100
160204800361601071011600061001600103006400361601082001600122004800361160000100
160204800361601071011600061001600103006400441601102001600142004800361160000100
160204800361601051011600041001600083006400361601082001600122004800421160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801201600181116000710160011306400441600202016001420480000116000010
160024800541600111116000010160000306400001600102016000020480000116000010
160025800731600551116004410160056306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480201116000010
160024800361600111116000010160000306400001600102016000020480000116000010