Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMLA (vector, by element, 8H)

Test 1: uops

Code:

  fcmla v0.8h, v1.8h, v2.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->1

Code:

  fcmla v0.8h, v1.8h, v2.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 3: Latency 1->2

Code:

  fcmla v0.8h, v0.8h, v1.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100003001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030015111000010
100244003310021211000020100007010285571002020100062030132111000010
100244003310021211000020100007010285571002020100042030012111000010
100244003310021211000020100007010285571002020100042030012111000010
100244003310021211000020100007010285571002020100042030012111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 4: Latency 1->3

Code:

  fcmla v0.8h, v1.8h, v0.h[1], #90
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10205400661010710310004102100303001028557101002001000620030018110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003071029107101332021004620030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100
10204400331010110110000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002230120111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcmla v0.8h, v8.8h, v9.h[1], #90
  movi v1.16b, 0
  fcmla v1.8h, v8.8h, v9.h[1], #90
  movi v2.16b, 0
  fcmla v2.8h, v8.8h, v9.h[1], #90
  movi v3.16b, 0
  fcmla v3.8h, v8.8h, v9.h[1], #90
  movi v4.16b, 0
  fcmla v4.8h, v8.8h, v9.h[1], #90
  movi v5.16b, 0
  fcmla v5.8h, v8.8h, v9.h[1], #90
  movi v6.16b, 0
  fcmla v6.8h, v8.8h, v9.h[1], #90
  movi v7.16b, 0
  fcmla v7.8h, v8.8h, v9.h[1], #90
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044049780109101800081008001230032005680113200800132002400391160000100
1602044010880110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400391160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002401381160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244403580019118000810800123032005680023208001320240000116000010
1600244130880011118000010800003032000080010208000020240000116000010
1600244042180011118000010800003032000080010208000020240000116000010
1600244041780011118000010800003032000080010208000020240000116000010
1600244042480011118000010800003032000080010208000020240000116000010
1600244039980011118000010800003032000080010208000020240000116000010
1600254058780054118004310800473032000080010208000020240000116000010
1600254057380055118004410800483032000080010208000020240000116000010
1600244041980011118000010800003032000080010208000020240000116000010
1600244040580011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  fcmla v0.8h, v16.8h, v17.h[1], #90
  fcmla v1.8h, v16.8h, v17.h[1], #90
  fcmla v2.8h, v16.8h, v17.h[1], #90
  fcmla v3.8h, v16.8h, v17.h[1], #90
  fcmla v4.8h, v16.8h, v17.h[1], #90
  fcmla v5.8h, v16.8h, v17.h[1], #90
  fcmla v6.8h, v16.8h, v17.h[1], #90
  fcmla v7.8h, v16.8h, v17.h[1], #90
  fcmla v8.8h, v16.8h, v17.h[1], #90
  fcmla v9.8h, v16.8h, v17.h[1], #90
  fcmla v10.8h, v16.8h, v17.h[1], #90
  fcmla v11.8h, v16.8h, v17.h[1], #90
  fcmla v12.8h, v16.8h, v17.h[1], #90
  fcmla v13.8h, v16.8h, v17.h[1], #90
  fcmla v14.8h, v16.8h, v17.h[1], #90
  fcmla v15.8h, v16.8h, v17.h[1], #90
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800661601061011600051001600093006400441601102001600142004800451160000100
160204800461601071011600061001600103006408601603142001602182004800391160000100
160204801891602081011601071001601113006400361601082001600122004803511160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204803391603161011602151001602193006400361601082001600122004801921160000100
160204800361601071011600061001600103006408601603142001602182004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100
160204800361601051011600041001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248014816001711160006010160010306400481600212016001420480000116000010
1600248007016001111160000010160000306402241600682016006520480000116000010
1621039845316199311781600827331138160102306401761600572016005220480039116000010
1600248004616001111160000010160000306402241600682016006620480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248005216001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600258007316005711160046010160058306400001600102016000020480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010