Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMLE (vector, zero, 4S)

Test 1: uops

Code:

  fcmle v0.4s, v0.4s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000

Test 2: Latency 1->2

Code:

  fcmle v0.4s, v0.4s, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010048110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100
1020420033101011011000010010000300509248101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100242003310021211000002010000705092471002020100002010000111000010
100242003310021211000002010000705092481002020100002010000111000010
100242003310021211000002010000705092481002020100002010000111000010
100242003310021211000002010000705092481002020100002010045111000010
100242003310021211000002010000705092481002020100002010000111000010
100242003310021211000002010000705092481002020100002010000111000010
100242003310021211000002010000705092481002020100002010000111000010
100242003310021211000002010000705092481002020100002010000111000010
100242003310021211000002010000705092481002020100002010000111000010
100242003310021211000002010000705092481002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  fcmle v0.4s, v8.4s, #0
  fcmle v1.4s, v8.4s, #0
  fcmle v2.4s, v8.4s, #0
  fcmle v3.4s, v8.4s, #0
  fcmle v4.4s, v8.4s, #0
  fcmle v5.4s, v8.4s, #0
  fcmle v6.4s, v8.4s, #0
  fcmle v7.4s, v8.4s, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020440070801051018000410080008300320036801082008001220080014180000100
8020440034801071018000610080010300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080014180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080014180000100
8020440034801071018000610080010300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024401268002721800062080010703200448003020800162080018118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010