Icestorm: FCMPE (scalar, D) measurements

Code:

  fcmpe d0, d1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1
1004	1034	1001	1	1000	1000	4000	1000	1000	2000	1

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fcmpe d0, d1
  fcsel d0, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	50010	1	10000	100
20205	40066	20109	101	20008	100	20034	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	0	30	0	1019248	20010	20	0	20000	20	50000	1	10000	10

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fcmpe d0, d1
  fcsel d1, d2, d3, eq

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	50015	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	50010	1	10000	100
20204	40033	20101	101	20000	100	20000	300	1019580	20134	200	20048	200	50010	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20006	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	50000	1	10000	10

Test 4: throughput

Count: 8

Code:

  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1
  fcmpe d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80204	80048	80101	101	80000	0	100	80001	300	320014	80103	200	80010	200	160016	1	100
80204	80034	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	160016	1	100
80204	80034	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	160016	1	100
80204	80034	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	160016	1	100
80204	80034	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	160016	1	100
80357	80997	80243	181	80019	43	171	80025	300	320014	80103	200	80010	200	160132	1	100
80204	80041	80102	101	80001	0	100	80003	300	320014	80103	200	80010	200	160016	1	100
80204	80034	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	160016	1	100
80204	80034	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	160016	1	100
80204	80034	80101	101	80000	0	100	80001	300	320005	80101	200	80008	200	160016	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80024	80034	80022	21	80001	0	20	80003	70	320010	80022	20	80008	20	160000	11	10
80024	80034	80021	21	80000	0	20	80000	66	320096	80045	20	80040	20	160000	11	10
80024	80034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	160000	11	10
80024	80034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	160000	11	10
80024	80034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	160000	11	10
80024	80034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	160000	11	10
80024	80034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	160000	11	10
80024	80034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	160072	11	10
80024	80034	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	160000	11	10
80025	80068	80038	21	80017	0	20	80023	70	320000	80020	20	80000	20	160000	11	10

FCMPE (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations