Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCMP (scalar, H)

Test 1: uops

Code:

  fcmp h0, h1
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001
10041034100111000100040001000100020001

Test 2: Latency 3->1

Chain cycles: 2

Code:

  fcmp h0, h1
  fcsel d0, d2, d3, eq
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20204400332010110120000100200003001019248201002002000420050015110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019580201342002004820050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20025400662001911200081020034301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205011011000010
20024400332001111200001020000301019248200102020000205011011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010

Test 3: Latency 3->2

Chain cycles: 2

Code:

  fcmp h0, h1
  fcsel d1, d2, d3, eq
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20205400662010910120008100200343001019248201002002000620050015110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100
20204400332010110120000100200003001019248201002002000420050010110000100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010
20024400332001111200001020000301019248200102020000205000011000010

Test 4: throughput

Count: 8

Code:

  fcmp h0, h1
  fcmp h0, h1
  fcmp h0, h1
  fcmp h0, h1
  fcmp h0, h1
  fcmp h0, h1
  fcmp h0, h1
  fcmp h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
802048003480101101800001008000130032001480103200800102001600161100
802048003480101101800001008000130032000580101200800082001600161100
802048003480101101800001008000130032000580101200800082001600161100
802048003480101101800001008000130032000580101200800082001600161100
802048003480101101800001008000130032000580101200800082001600161100
802048003480101101800001008000130032000580101200800082001600161100
802048003480101101800001008000130032008880123200800362001600161100
802048003480101101800001008000130032000580101200800082001600161100
802048003480101101800001008000130032000580101200800082001600161100
802048003480101101800001008000130032000580101200800082001600161100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? int retires (ef)
8002480049800212180000208000270320018800242080010201600721110
8002480034800212180000208000070320000800202080000201600001110
8002480034800212180000208000066320092800442080035201600161110
8002480034800212180000208000070320000800202080000201600721110
8002480034800212180000208000070320000800202080000201600001110
8002480034800212180000208000069320092800442080036201600001110
8002480034800212180000208000070320000800202080000201600001110
8002480034800212180000208000070320000800202080000201600721110
8002480034800212180000208000070320000800202080000201600001110
8002480034800212180000208000066320174800662080064201600001110