Icestorm: FCSEL (scalar, D) measurements

Code:

  fcsel d0, d0, d1, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	30018	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30144	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10025	20066	10029	21	10008	20	10034	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 2: uops

Code:

  fcsel d0, d1, d0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000

Test 3: Latency 1->3

Code:

  fcsel d0, d1, d0, lt

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509780	10056	20	10040	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->4

Chain cycles: 2

Code:

  fcsel d0, d1, d2, lt
  fcmp d0, d3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20201	201	20000	200	20000	700	1019247	20200	200	20006	200	50015	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100
20204	40033	20201	201	20000	200	20000	700	1019248	20200	200	20004	200	50010	101	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20021	21	20000	20	20000	70	1019247	20020	20	20006	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50000	11	10000	10
20024	40033	20021	21	20000	20	20000	70	1019248	20020	20	20000	20	50110	11	10000	10

Test 5: throughput

Count: 8

Code:

  fcsel d0, d8, d9, lt
  fcsel d1, d8, d9, lt
  fcsel d2, d8, d9, lt
  fcsel d3, d8, d9, lt
  fcsel d4, d8, d9, lt
  fcsel d5, d8, d9, lt
  fcsel d6, d8, d9, lt
  fcsel d7, d8, d9, lt

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40037	80105	101	80004	100	80009	300	399252	80110	200	80014	200	240039	1	80000	100
80204	40045	80107	101	80006	100	80010	300	399242	80108	200	80012	200	240036	1	80000	100
80204	40035	80105	101	80004	100	80008	300	399242	80108	200	80012	200	240036	1	80000	100
80204	40035	80105	101	80004	100	80008	300	399242	80108	200	80012	200	240036	1	80000	100
80204	40035	80105	101	80004	100	80008	300	399242	80108	200	80012	200	240180	1	80000	100
80204	40035	80105	101	80004	100	80008	300	399242	80108	200	80012	200	240036	1	80000	100
80204	40035	80105	101	80004	100	80008	300	399242	80108	200	80012	200	240036	1	80000	100
80204	40035	80105	101	80004	100	80008	300	399242	80108	200	80012	200	240036	1	80000	100
80204	40035	80105	101	80004	100	80008	300	399242	80108	200	80012	200	240036	1	80000	100
80204	40035	80105	101	80004	100	80008	300	404072	80154	200	80064	200	240036	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40593	80027	21	80006	20	80010	68	376000	80020	20	80000	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	384000	80020	20	80000	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	369830	80076	20	80066	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	384000	80020	20	80000	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	384000	80020	20	80000	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	384000	80020	20	80000	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	384000	80020	20	80000	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	384000	80020	20	80000	20	240000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	384000	80020	20	80000	20	240138	11	80000	10
80024	40035	80021	21	80000	20	80000	67	381561	80069	20	80049	20	240000	11	80000	10

FCSEL (scalar, D)

Test 1: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 2: uops

1000 unrolls and 1 iteration

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations