Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTAS (scalar, S to S)

Test 1: uops

Code:

  fcvtas s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	76247	1031	1038	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fcvtas s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	10006	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	202	10046	2	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10205	30066	10109	103	10006	102	10031	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	769247	10131	200	10044	200	10048	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	10000	11	10000	10
10024	30152	10029	21	10008	20	10033	70	768905	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	68	768902	10086	20	10078	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	10120	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	73	768698	10086	22	10081	20	10038	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	10000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  fcvtas s0, s8
  fcvtas s1, s8
  fcvtas s2, s8
  fcvtas s3, s8
  fcvtas s4, s8
  fcvtas s5, s8
  fcvtas s6, s8
  fcvtas s7, s8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40058	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80107	101	80006	100	80010	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80107	101	80006	100	80010	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320044	80110	200	80014	200	80012	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80025	40200	80063	21	80042	20	80054	70	320052	80032	20	80018	20	80000	11	80000	10
80024	40054	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10