Icestorm: FCVTAS (scalar, S to W) measurements

Code:

  fcvtas w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  fcvtas w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546786	2578206	30100	200	10002	20004	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546828	2578258	30100	200	10001	20003	200	10020	20040	10002	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	202	10021	20040	10003	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546828	2578258	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100120	40101	10101	20000	10000	100	20000	10000	300	1547090	2578674	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100034	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10001	20003	20	10002	20004	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10016	30	1546725	2578839	30056	20	10017	20036	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10017	30	1547831	2580607	30057	20	10017	20036	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100126	40020	10013	20005	10002	10	20030	10017	30	1546546	2578527	30057	20	10019	20041	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100038	40011	10011	20000	10000	10	20000	10000	30	1546817	2578960	30010	20	10000	20000	20	10018	20035	10003	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  fcvtas w0, s8
  fcvtas w1, s8
  fcvtas w2, s8
  fcvtas w3, s8
  fcvtas w4, s8
  fcvtas w5, s8
  fcvtas w6, s8
  fcvtas w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80057	240103	80101	160002	100	160008	300	880290	160158	200	160068	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880290	160158	200	160068	200	160012	80001	80000	80100
160205	80074	240155	80115	160040	100	160058	300	880053	160110	200	160014	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80040	240013	80011	160002	0	10	160008	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80100	240084	80033	160051	0	10	160054	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
114778	76341	169910	58029	110485	1396	2981	110502	30	880338	160072	20	160066	20	0	160012	80001	0	80000	80010
160024	80108	240084	80033	160051	0	10	160054	30	880290	160068	20	160068	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	0	160054	80023	0	80000	80010
160024	80097	240084	80033	160051	0	10	160054	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80101	240084	80033	160051	0	10	160054	30	880297	160064	20	160054	20	0	160066	80015	0	80000	80010
160025	80074	240065	80025	160040	0	10	160058	30	880594	160118	20	160108	20	0	160000	80001	0	80000	80010

FCVTAS (scalar, S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations