Icestorm: FCVTMU (scalar, D to W) measurements

Code:

  fcvtmu w0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu w0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0127

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100313	40130	10109	20015	10006	102	20090	10034	300	1548583	2581266	30194	200	10036	20076	202	10053	20113	10008	10000	10000	10100
30204	100305	40128	10107	20014	10007	100	20090	10035	300	1548679	2581402	30195	200	10037	20075	200	10056	20112	10007	10000	10000	10100
30204	100216	40123	10109	20009	10005	104	20060	10036	300	1548497	2581038	30196	200	10038	20078	200	10019	20041	10003	10000	10000	10100
30204	100306	40128	10107	20013	10008	100	20090	10034	300	1548658	2581396	30194	200	10036	20076	200	10036	20076	10005	10000	10000	10100
30205	100522	40154	10114	20025	10015	102	20178	10052	306	1549644	2582893	30244	202	10054	20111	200	10038	20078	10005	10000	10000	10100
30204	100122	40110	10103	20005	10002	100	20030	10036	300	1548651	2581278	30196	200	10038	20074	204	10074	20149	10011	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10086	313	1551684	2586453	30340	204	10090	20183	200	10072	20150	10009	10000	10000	10100
30204	100401	40137	10109	20018	10010	100	20120	10087	307	1551301	2585677	30339	202	10092	20184	204	10126	20256	10017	10000	10000	10100
30204	100490	40150	10115	20023	10012	104	20150	10071	307	1550798	2584890	30293	202	10076	20150	200	10089	20183	10011	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10051	300	1549862	2583303	30241	200	10052	20112	202	10036	20076	10006	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546336	2578206	30010	20	10002	20004	20	10000	20000	10001	10000	10000	10010
30024	100625	40065	10023	20028	10014	10	20180	10068	30	1550264	2584820	30198	20	10068	20144	20	10000	20000	10001	10000	10000	10010
30024	100306	40038	10017	20012	10009	10	20090	10018	30	1547343	2579827	30058	20	10019	20041	22	10035	20073	10006	10000	10000	10010
30024	101740	40173	10047	20081	10045	10	20540	10104	30	1552935	2589218	30294	20	10105	20216	20	10018	20035	10003	10000	10000	10010
30024	100213	40029	10015	20008	10006	10	20060	10036	30	1548202	2581330	30106	20	10038	20074	20	10055	20110	10007	10000	10000	10010
30024	100137	40020	10013	20005	10002	10	20030	10053	30	1548966	2582665	30153	20	10054	20108	20	10072	20144	10008	10000	10000	10010
30024	100414	40047	10019	20017	10011	10	20120	10017	30	1551767	2586613	30057	20	10017	20036	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100120	40020	10013	20004	10003	10	20030	10000	30	1546346	2578206	30010	20	10000	20000	20	10199	20396	10023	10000	10000	10010
30024	100459	40056	10021	20024	10011	10	20150	10000	30	1546414	2578310	30010	20	10000	20000	20	10053	20112	10005	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  fcvtmu w0, d8
  fcvtmu w1, d8
  fcvtmu w2, d8
  fcvtmu w3, d8
  fcvtmu w4, d8
  fcvtmu w5, d8
  fcvtmu w6, d8
  fcvtmu w7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80057	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880278	160156	200	0	160066	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	100	160008	0	300	0	880041	160108	200	0	160012	200	160012	80001	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80062	240013	80011	160002	10	160008	30	880041	160018	20	160012	20	160012	80001	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160054	80015	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160025	80074	240065	80025	160040	10	160058	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	160068	80015	80000	80010

FCVTMU (scalar, D to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations