Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTMU (scalar, H to W)

Test 1: uops

Code:

  fcvtmu w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3020410003340101101012000010000100200001000030015468022578232301002001000220004200100022000410001100001000010100
3020410003340101101012000010000100200001000030015467962578206301002001000120003200100192004110002100001000010100
3020410003340101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003540101101012000010000100200001000030015469252578414301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020510006440107101022000410001100200301000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
300241001624002210015200051000212200301000030154633625782063001020100022000420100022000410001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241001534002010013200041000310200301000030154634625782063001020100002000020100002000010001100001000010010
300241000444001110011200001000010200001000030154650625784663001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241001264002010013200041000310200301000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001001730154654625785273005720100192004120100002000010001100001000010010
300241000324001110011200001000010200001000030154644225783623001020100002000020100172003610003100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000334001110011200001000010200001001730154740025799833005720100172003620100002000010001100001000010010

Test 3: throughput

Count: 8

Code:

  fcvtmu w0, h8
  fcvtmu w1, h8
  fcvtmu w2, h8
  fcvtmu w3, h8
  fcvtmu w4, h8
  fcvtmu w5, h8
  fcvtmu w6, h8
  fcvtmu w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602048005724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160068800158000080100
1602048004624010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160068800158000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002480040240013800111600021016000830880041160018201600122001600688001508000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010