Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTNU (vector, 2S)

Test 1: uops

Code:

  fcvtnu v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000

Test 2: Latency 1->2

Code:

  fcvtnu v0.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000620010006110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010004111000010
10024300331002121100002010000707692471005120100402010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  fcvtnu v0.2s, v8.2s
  fcvtnu v1.2s, v8.2s
  fcvtnu v2.2s, v8.2s
  fcvtnu v3.2s, v8.2s
  fcvtnu v4.2s, v8.2s
  fcvtnu v5.2s, v8.2s
  fcvtnu v6.2s, v8.2s
  fcvtnu v7.2s, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
802044005580107101800061008001030032003680108200800122000800121080000100
802044004480105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024400978002721800062080010703200448003020800162080000118000010
80024400358002121800002080000703200528003220800182080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010