Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTN (vector, 2D)

Test 1: uops

Code:

  fcvtn v0.2s, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004308410091100810337590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000

Test 2: Latency 1->2

Code:

  fcvtn v0.2s, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010044110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  fcvtn v0.2s, v8.2d
  fcvtn v1.2s, v8.2d
  fcvtn v2.2s, v8.2d
  fcvtn v3.2s, v8.2d
  fcvtn v4.2s, v8.2d
  fcvtn v5.2s, v8.2d
  fcvtn v6.2s, v8.2d
  fcvtn v7.2s, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020440055801051018000410080008300320036801082008001220080012180000100
8020440044801051018000410080008300320044801102008001420080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320216801562008006420080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100
8020440035801051018000410080008300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024402178002721800062080010703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010