Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, D to X)

Test 1: uops

Code:

  fcvtps x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3020410003240101101012000010000100200001000030015467862578206301002001000220004200100012000310001100001000010100
3020410003240101101012000010000100200001001830015470462578613301462001002020040200100012000310001100001000010100
3020410041340139101112001710011102201201000030015469282578414301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100192004110002100001000010100
3020510011340109101042000310002102200281000030015467962578206301002001000120003200100202004010002100001000010100
3020410003640101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100202004010002100001000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
300251002954003510016200131000610200901001830154650425784833005620100212004120100202004010002100001000010010
300241000804001110011200001000010200001003330154753525801483010320100362007720100542010910004100001000010010
300281003564003510015200151000510201181006737155131425862143019522100722014820101102022010008100001000010010
300291003694004110016200181000710201461008230155058725850973024020100882018420100722014410005100001000010010
300281003654003510015200131000710201141008230155085725855133024020100882018420100732014910005100001000010010
300281003024003510015200151000510201181006630154969525836403019220100712014620100722014810005100001000010010
300281003264003510015200141000610201161008330155004925841773023720100892018120100012000310001100001000010010
300241000354001110011200001000010200001000030154637825782583001020100002000020100012000310001100001000010010
300241000364001110011200001000010200001000030154636325782323001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010

Test 3: throughput

Count: 8

Code:

  fcvtps x0, d8
  fcvtps x1, d8
  fcvtps x2, d8
  fcvtps x3, d8
  fcvtps x4, d8
  fcvtps x5, d8
  fcvtps x6, d8
  fcvtps x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160012800018000080100
1602048003724010380101160002100160008300880041160108200160012200160068800158000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024800652400138001116000210160008308800411600182016001220160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010
160024800372400118001116000010160000308800001600102016000020160000800018000080010