Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, H to H)

Test 1: uops

Code:

  fcvtps h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000

Test 2: Latency 1->2

Code:

  fcvtps h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1020430033101011011000001001000030076890510100200100062000100061010000100
1020430033101011011000001001000030076890510100200100042000100041010000100
1020430033101011011000001001000030076890510100200100042000100061010000100
1020430033101011011000001001000030076890510100200100042000100041010000100
1020430033101011011000001001000030076890510100200100042000100041010000100
1020430033101011011000001001000030076890510100200100042000100041010000100
1020430033101011011000001001000030076890510100200100042000100041010000100
1020430033101011011000001001000030076890510100200100042000100041010000100
1020430033101011011000001001000030076890510100200100042000100041010000100
1020430033101011011000001001000030076890510100200100042000100041010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010
10024300331002121100002010000707689051002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  fcvtps h0, h8
  fcvtps h1, h8
  fcvtps h2, h8
  fcvtps h3, h8
  fcvtps h4, h8
  fcvtps h5, h8
  fcvtps h6, h8
  fcvtps h7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400868010710180006010080010300320036801082008001220080014180000100
80204400538010510180004010080008300320036801082008001220080012180000100
80204400358010710180006010080010300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8002440182800272180006208001070320044800302080016200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010
8002440035800212180000208000070320000800202080000200800001108000010