Icestorm: FCVTZS (scalar, fixed-point, H to W) measurements

Code:

  fcvtzs w0, h0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2054	1015	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, h0, #3
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546786	2578206	30100	200	10002	20004	200	10002	20004	10001	10000	10000	10100
30204	100402	40137	10109	20016	10012	100	20120	10000	300	1546862	2578310	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100140	40110	10103	20004	10003	100	20030	10105	307	1553860	2590068	30387	202	10111	20222	200	10052	20112	10007	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	202	10020	20040	10003	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100038	40011	10011	20000	10000	10	20000	10000	30	1546431	2578336	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10018	30	1546525	2578483	30056	20	10020	20040	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, h8, #3
  fcvtzs w1, h8, #3
  fcvtzs w2, h8, #3
  fcvtzs w3, h8, #3
  fcvtzs w4, h8, #3
  fcvtzs w5, h8, #3
  fcvtzs w6, h8, #3
  fcvtzs w7, h8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80177	240250	80145	160105	100	160118	300	880350	160164	200	160068	4880	3023	160174	82246	1229	80002	82578
160204	80106	240177	80123	160054	100	160064	300	881229	160324	200	160228	390	216	160228	80190	106	80001	80254
160205	80134	240228	80137	160091	100	160112	300	880338	160162	200	160066	200	0	160012	80001	0	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	0	160012	80001	0	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	0	160012	80001	0	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	0	160012	80001	0	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	0	160012	80001	0	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	0	160066	80015	0	80000	80100
160204	80037	240103	80101	160002	100	160008	300	880041	160108	200	160012	200	0	160068	80015	0	80000	80100
160204	80047	240104	80101	160003	100	160010	300	880041	160108	200	160012	200	0	160012	80001	0	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80061	240013	80011	160002	10	160008	30	880041	160018	20	160012	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880290	160068	20	160068	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880278	160066	20	160066	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010
160024	80037	240011	80011	160000	10	160000	30	880000	160010	20	160000	20	0	160000	80001	0	80000	80010

FCVTZS (scalar, fixed-point, H to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations