Icestorm: FCVTZS (scalar, integer, H to W) measurements

Code:

  fcvtzs w0, h0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000
2004	1037	3001	1001	2000	2000	11000	2000	2000	2000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, h0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546786	2578206	30100	200	10002	20004	200	10002	20004	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30205	100062	40107	10102	20003	10002	100	20028	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546893	2578362	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30205	100062	40107	10102	20003	10002	100	20028	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	1546796	2578206	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100041	40011	10011	20000	10000	10	20000	10000	30	1546336	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10020	20040	10002	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546397	2578284	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10017	30	1547242	2579671	30057	20	10017	20036	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546590	2578596	30010	20	10000	20000	20	10001	20003	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	1546346	2578206	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, h8
  fcvtzs w1, h8
  fcvtzs w2, h8
  fcvtzs w3, h8
  fcvtzs w4, h8
  fcvtzs w5, h8
  fcvtzs w6, h8
  fcvtzs w7, h8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160205	80084	240154	80115	160039	0	100	160056	300	880278	160156	200	160066	200	160012	80001	80000	80100
160204	80046	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	302	880290	160160	202	160066	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100
160204	80037	240103	80101	160002	0	100	160008	300	880041	160108	200	160012	200	160012	80001	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80057	240013	80011	160002	0	10	160008	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880290	160068	20	160068	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880000	160010	20	160000	20	160000	80001	80000	80010
160024	80037	240011	80011	160000	0	10	160000	30	880290	160068	20	160068	20	160000	80001	80000	80010

FCVTZS (scalar, integer, H to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations