Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, fixed-point, H to H)

Test 1: uops

Code:

  fcvtzu h0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000
1004303310011100010007590510001000100011000

Test 2: Latency 1->2

Code:

  fcvtzu h0, h0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000620010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030707692471013320201004220010005110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100
1020430033101011011000010010000030007689051010020001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10024300331002121100000201000070768905100202010000200100001101000010
10024300331002121100000201000070768905100202010000200100001101000010
10024300331002121100000201000070768905100202010000200100001101000010
10024300331002121100000201000070768905100202010000200100001101000010
10024300331002121100000201000070768905100202010000200100001101000010
10024300331002121100000201000070768905100202010000200100441101000010
10024300331002121100000201000070768905100202010000200100001101000010
10024300331002121100000201000069768905100202010004403739541006317502022100232505
10024300331002121100000201000070768905100202010004200100001101000010
12011346131233514901000683915841003170768905100202010000200100001101000010

Test 3: throughput

Count: 8

Code:

  fcvtzu h0, h8, #3
  fcvtzu h1, h8, #3
  fcvtzu h2, h8, #3
  fcvtzu h3, h8, #3
  fcvtzu h4, h8, #3
  fcvtzu h5, h8, #3
  fcvtzu h6, h8, #3
  fcvtzu h7, h8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400588010710180006010080010300320036801082008001220080012180000100
80204400358010710180006010080010300320044801102008001420080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010710180006010080010300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100
80204400358010510180004010080008300320036801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024401758002721800062080010703200448003020800162080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80025400708006321800422080054703200008002020800002080000118000010
80024400358002121800002080000703200528003220800182080049118000010
80024400358002121800002080000703200008002020800002080394118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080049118000010
80024400358002121800002080000703200008002020800002080000118000010