Icestorm: FCVTZU (scalar, fixed-point, H to H) measurements

Code:

  fcvtzu h0, h0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  fcvtzu h0, h0, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10006	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	307	0	769247	10133	202	0	10042	200	10005	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	10000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	10000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	10000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	10000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	10000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	10044	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	10000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	69	768905	10020	20	10004	4037	3954	10063	1750	2022	10023	2505
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10004	20	0	10000	11	0	10000	10
12011	34613	12335	1490	10006	839	1584	10031	70	768905	10020	20	10000	20	0	10000	11	0	10000	10

Test 3: throughput

Count: 8

Code:

  fcvtzu h0, h8, #3
  fcvtzu h1, h8, #3
  fcvtzu h2, h8, #3
  fcvtzu h3, h8, #3
  fcvtzu h4, h8, #3
  fcvtzu h5, h8, #3
  fcvtzu h6, h8, #3
  fcvtzu h7, h8, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40058	80107	101	80006	0	100	80010	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80107	101	80006	0	100	80010	300	320044	80110	200	80014	200	80012	1	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80107	101	80006	0	100	80010	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40175	80027	21	80006	20	80010	70	320044	80030	20	80016	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80025	40070	80063	21	80042	20	80054	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320052	80032	20	80018	20	80049	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80394	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80049	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10

FCVTZU (scalar, fixed-point, H to H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations