Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZU (scalar, integer, H to W)

Test 1: uops

Code:

  fcvtzu w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000
20041037300110012000200011000200020002000100110001000

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzu w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3020410003240101101012000010000100200001001730015469572578483301452001001920038200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020510006440107101022000410001100200301000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100
3020410003240101101012000010000100200001000030015467962578206301002001000120003200100012000310001100001000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
300241000344001110011200001000010200001000030154633625782063001020100002000020100002000010001100001000010010
300251000644001710012200041000110200301000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010
300241000324001110011200001000010200001000030154634625782063001020100002000020100002000010001100001000010010

Test 3: throughput

Count: 8

Code:

  fcvtzu w0, h8
  fcvtzu w1, h8
  fcvtzu w2, h8
  fcvtzu w3, h8
  fcvtzu w4, h8
  fcvtzu w5, h8
  fcvtzu w6, h8
  fcvtzu w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
16020480057240103801011600020100160008300880041160108200160012200160012800018000080100
16020480037240103801011600020100160008300881229160324200160228200160012800018000080100
16020480037240103801011600020100160008300880338160162200160066200160012800018000080100
16020480101240176801231600530100160062300880041160108200160012200160066800238000080100
16020480037240103801011600020100160008300880350160164200160068200160012800018000080100
16020480159240249801451601040100160116300880041160108200160012200160068800238000080100
16020480037240103801011600020100160008307880922160270202160172200160228800898000080100
16020480607240396801891602070100160226300881823160432200160336200160012800018000080100
16020480037240103801011600020100160008300880290160158200160068200160012800018000080100
16020480037240103801011600020100160008300880041160108200160012200160012800018000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002480057240013800111600021016000830880000160010201600002001600548001508000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
160025800742400658002516004010160058308800001600102016000016741179148166748046497405975153
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010
16002480037240011800111600001016000030880000160010201600002001600008000108000080010