Icestorm: FDIV (scalar, D) measurements

Code:

  fdiv d0, d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000
1004	10033	1001	1	1000	1000	128069	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fdiv d0, d0, d1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10006	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289241	10115	200	10032	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10004	200	20008	1	10000	100
10205	100066	10103	101	10002	100	10015	300	1289069	10100	200	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	300	1289069	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10025	100066	10023	21	10002	20	10015	70	1289069	10020	20	10004	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20056	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	0	20000	11	0	10000	10

Test 3: Latency 1->3

Code:

  fdiv d0, d1, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10006	200	20012	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289413	10130	200	0	10053	200	20008	1	10000	100
10205	100066	10103	101	10002	100	10015	0	300	0	1289069	10100	200	0	10004	200	20012	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	20056	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	20008	1	10000	100
10204	100033	10101	101	10000	100	10000	0	300	0	1289069	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	67	1289241	10035	20	10029	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10004	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10
10024	100033	10021	21	10000	20	10000	70	1289069	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  fdiv d0, d8, d9
  fdiv d1, d8, d9
  fdiv d2, d8, d9
  fdiv d3, d8, d9
  fdiv d4, d8, d9
  fdiv d5, d8, d9
  fdiv d6, d8, d9
  fdiv d7, d8, d9

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	80056	80101	101	80000	100	80001	300	320014	80103	200	80010	200	160020	1	80000	100
80204	80042	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80042	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80042	80101	101	80000	100	80001	300	320120	80131	200	80046	200	160088	1	80000	100
80204	80042	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80042	80101	101	80000	100	80001	300	320014	80103	200	80010	200	160016	1	80000	100
80204	80049	80102	101	80001	100	80003	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80049	80102	101	80001	100	80003	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80042	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80042	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	80057	80021	21	80000	20	80002	70	320010	80022	20	80008	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80042	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10

FDIV (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations