Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FDIV (scalar, H)

Test 1: uops

Code:

  fdiv h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000
1004703310011100010008934010001000200011000

Test 2: Latency 1->2

Code:

  fdiv h0, h0, h1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020470033101011011000010010000300899340101002001000420020012110000100
1020470033101011011000010010000300899340101002001000620020008110000100
1020470033101011011000010010000300899340101002001000420020012110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899509101162001002820020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10025700661002421100032010016708993401002020100042020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020056111000010
10024700331002121100002010000708993401002020100002020058111000010
10024700331002121100002010000708993401002020100042020000111000010
10024700331002121100002010000708993401002020100002020000111000010

Test 3: Latency 1->3

Code:

  fdiv h0, h1, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020470033101011011000010010000300899340101002001000620020012110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020570066101041011000310010016300899340101002001000620020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100
1020470033101011011000010010000300899509101162001002820020008110000100
1020470033101011011000010010000300899340101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024700331002121100002010000708993401002020100042020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020008111000010
10024700331002121100002010000708993401002020100002020000111000010
10024700331002121100002010000708993401002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  fdiv h0, h8, h9
  fdiv h1, h8, h9
  fdiv h2, h8, h9
  fdiv h3, h8, h9
  fdiv h4, h8, h9
  fdiv h5, h8, h9
  fdiv h6, h8, h9
  fdiv h7, h8, h9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
802048005380101101800000100800013003200148010320080010200160016180000100
802048003980101101800000100800013003200148010320080010200160016180000100
802048003980101101800000100800013003200058010120080008200160016180000100
802048003980101101800000100800013003200058010120080008200160016180000100
802048003980101101800000100800013003200058010120080008200160016180000100
802048003980101101800000100800013003200058010120080008200160020180000100
802048004680102101800010100800033003200058010120080008200160016180000100
802048003980101101800000100800013003200058010120080008200160016180000100
802048003980101101800000100800013003200058010120080008200160016180000100
802048003980101101800000100800013003200058010120080008200160016180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800248005480021218000020800027032001880024208001020160000118000010
800248003980021218000020800007032000080020208000020160000118000010
800248003980021218000020800007032000080020208000020160000118000010
800248003980021218000020800007032000080020208000020160000118000010
800248003980021218000020800007032000080020208000020160000118000010
800258007880045218002420800307032000080020208000020160000118000010
800248003980021218000020800007032000080020208000020160000118000010
800248003980021218000020800007032000080020208000020160000118000010
800248003980021218000020800007032000080020208000020160000118000010
800248003980021218000020800007032000080020208000020160000118000010