Icestorm: FDIV (vector, 2D) measurements

Code:

  fdiv v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000
1004	11033	1001	1	1000	1000	140978	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fdiv v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 11.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	110033	10101	101	10000	0	100	10000	0	300	0	1418978	10100	200	0	10006	202	0	20052	2	0	10000	100
10204	110033	10101	101	10000	0	100	10000	0	300	0	1419252	10115	200	0	10027	200	0	20008	1	0	10000	100
10204	110033	10101	101	10000	0	100	10000	0	300	0	1418978	10100	200	0	10004	200	0	20008	1	0	10000	100
10204	110033	10101	101	10000	0	100	10000	0	300	0	1418978	10100	200	0	10004	200	0	20008	1	0	10000	100
10204	110080	10104	101	10003	0	100	10015	0	300	0	1418978	10100	200	0	10004	200	0	20008	1	0	10000	100
10204	110033	10101	101	10000	0	100	10000	0	300	0	1419424	10130	200	0	10052	200	0	20008	1	0	10000	100
10205	110066	10105	103	10002	0	102	10015	0	300	0	1418978	10100	200	0	10004	200	0	20008	1	0	10000	100
10204	110033	10101	101	10000	0	100	10000	0	300	0	1418978	10100	200	0	10004	200	0	20008	1	0	10000	100
10204	110033	10101	101	10000	0	100	10000	0	300	0	1418978	10100	200	0	10004	200	0	20008	1	0	10000	100
10204	110033	10101	101	10000	0	100	10000	0	300	0	1418978	10100	200	0	10004	200	0	20008	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 11.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10004	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	69	1419150	10035	20	10032	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10025	110066	10023	21	10002	20	10015	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  fdiv v0.2d, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 11.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10205	110066	10105	103	10002	102	10015	722	30355	10401	1419128	11929	1738	851	10026	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10006	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20064	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20008	1	10000	100
10204	110033	10101	101	10000	100	10000	0	300	0	1418978	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 11.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10006	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10025	110066	10023	21	10002	20	10015	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10025	110066	10023	21	10002	20	10015	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1418978	10020	20	10000	20	20000	11	10000	10
10024	110033	10021	21	10000	20	10000	70	1419150	10035	20	10028	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  fdiv v0.2d, v8.2d, v9.2d
  fdiv v1.2d, v8.2d, v9.2d
  fdiv v2.2d, v8.2d, v9.2d
  fdiv v3.2d, v8.2d, v9.2d
  fdiv v4.2d, v8.2d, v9.2d
  fdiv v5.2d, v8.2d, v9.2d
  fdiv v6.2d, v8.2d, v9.2d
  fdiv v7.2d, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	160042	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80006	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	2000019	80125	200	0	80040	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	2000019	80125	200	0	80040	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	2000019	80125	200	0	80036	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	160008	1	80000	100
80204	160042	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	160008	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	160042	80021	21	80000	20	80000	70	1999768	80020	20	80006	20	160000	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160074	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160136	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160042	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160042	80021	21	80000	20	80000	66	2000019	80045	20	80037	20	160000	11	80000	10

FDIV (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations