Icestorm: FDIV (vector, 2S) measurements

Code:

  fdiv v0.2s, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fdiv v0.2s, v0.2s, v1.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10006	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100
10205	80066	10103	101	10002	100	10015	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029524	10116	200	0	10028	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	0	300	0	1029250	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10006	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  fdiv v0.2s, v1.2s, v0.2s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20012	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20056	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10025	80066	10023	21	10002	20	10015	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  fdiv v0.2s, v8.2s, v9.2s
  fdiv v1.2s, v8.2s, v9.2s
  fdiv v2.2s, v8.2s, v9.2s
  fdiv v3.2s, v8.2s, v9.2s
  fdiv v4.2s, v8.2s, v9.2s
  fdiv v5.2s, v8.2s, v9.2s
  fdiv v6.2s, v8.2s, v9.2s
  fdiv v7.2s, v8.2s, v9.2s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	80040	80101	101	80000	100	80002	300	320014	80103	200	80010	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80205	80080	80126	101	80025	100	80031	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80040	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	80040	80021	21	80000	0	20	80002	70	320018	80024	20	80010	20	0	160000	11	0	80000	10
80024	80040	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	0	160000	11	0	80000	10
80024	80040	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	0	160000	11	0	80000	10
80025	80080	80044	21	80023	0	20	80029	70	320000	80020	20	80000	20	0	160000	11	0	80000	10
80024	80040	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	0	160088	11	0	80000	10
80024	80040	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	0	160000	11	0	80000	10
80025	80080	80046	21	80025	0	20	80031	70	320000	80020	20	80000	20	0	160000	11	0	80000	10
80024	80040	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	0	160000	11	0	80000	10
80024	80040	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	0	160000	11	0	80000	10
80024	80040	80021	21	80000	0	20	80000	70	320000	80020	20	80000	20	0	160000	11	0	80000	10

FDIV (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations