Icestorm: FDIV (vector, 4H) measurements

Code:

  fdiv v0.4h, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000
1004	7033	1001	1	1000	1000	89340	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fdiv v0.4h, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10006	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10205	70066	10104	101	10003	100	10016	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899509	10116	200	10028	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20062	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  fdiv v0.4h, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10006	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10205	70066	10104	101	10003	100	10016	300	899340	10100	200	10006	200	20056	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100
10204	70033	10101	101	10000	100	10000	300	899340	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10004	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899509	10036	20	10028	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899509	10036	20	10028	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10
10024	70033	10021	21	10000	20	10000	70	899340	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  fdiv v0.4h, v8.4h, v9.4h
  fdiv v1.4h, v8.4h, v9.4h
  fdiv v2.4h, v8.4h, v9.4h
  fdiv v3.4h, v8.4h, v9.4h
  fdiv v4.4h, v8.4h, v9.4h
  fdiv v5.4h, v8.4h, v9.4h
  fdiv v6.4h, v8.4h, v9.4h
  fdiv v7.4h, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	80053	80101	101	80000	100	80001	300	320014	80103	200	80010	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320108	80128	200	80042	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320005	80101	200	80008	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320108	80128	200	80042	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	320116	80130	200	80044	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	80054	80021	21	80000	20	80002	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80039	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80025	80078	80044	21	80023	20	80029	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80039	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80039	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80039	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80039	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80039	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	80039	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160080	11	80000	10
80024	80039	80021	21	80000	20	80002	70	320000	80020	20	80000	20	160000	11	80000	10

FDIV (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations