Icestorm: FDIV (vector, 8H) measurements

Code:

  fdiv v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000
1004	8033	1001	1	1000	1000	102250	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fdiv v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10006	200	20008	1	10000	100
10205	80066	10103	101	10002	100	10015	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100
10205	80066	10103	101	10002	100	10015	300	1029250	10100	200	10004	200	20008	1	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10006	20	20012	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20064	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20054	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  fdiv v0.8h, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10006	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100
10204	80033	10101	101	10000	100	10000	300	1029250	10100	200	10004	200	0	20008	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10006	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20056	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10
10024	80033	10021	21	10000	20	10000	70	1029250	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  fdiv v0.8h, v8.8h, v9.8h
  fdiv v1.8h, v8.8h, v9.8h
  fdiv v2.8h, v8.8h, v9.8h
  fdiv v3.8h, v8.8h, v9.8h
  fdiv v4.8h, v8.8h, v9.8h
  fdiv v5.8h, v8.8h, v9.8h
  fdiv v6.8h, v8.8h, v9.8h
  fdiv v7.8h, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	160039	80101	101	80000	100	80000	0	300	0	1999982	80124	200	0	80036	200	0	160008	1	0	80000	100
80204	160039	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	0	160008	1	0	80000	100
80204	160039	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	0	160008	1	0	80000	100
80204	160039	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	0	160008	1	0	80000	100
80205	160078	80112	101	80011	100	80024	0	300	0	1999982	80124	200	0	80040	200	0	160008	1	0	80000	100
80204	160039	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	0	160008	1	0	80000	100
80204	160039	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	0	160072	1	0	80000	100
80204	160039	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	0	160072	1	0	80000	100
80204	160039	80101	101	80000	100	80000	0	300	0	1999769	80100	200	0	80004	200	0	160072	1	0	80000	100
80205	160078	80112	101	80011	100	80024	0	300	0	1999769	80100	200	0	80004	200	0	160008	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80004	20	160000	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80025	160078	80032	21	80011	20	80024	70	1999768	80020	20	80000	20	160000	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160072	11	80000	10
80024	160039	80021	21	80000	20	80000	70	1999769	80020	20	80000	20	160000	11	80000	10

FDIV (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations