Icestorm: FJCVTZS measurements

Code:

  fjcvtzs w0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000
2004	2150	3001	1001	2000	2000	25203	2000	2000	2000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  fjcvtzs w0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100032	40101	10101	20000	10000	100	20000	10011	300	877704	1279649	30126	200	10014	20028	200	10002	20004	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30205	100062	40107	10102	20003	10002	100	20015	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100
30204	100032	40101	10101	20000	10000	100	20000	10000	300	877614	1279516	30100	200	10001	20003	200	10001	20003	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100034	40011	10011	20000	10000	10	20000	10000	30	877152	1279516	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	877164	1279516	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	877164	1279516	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10010	30	877748	1280312	30035	20	10011	20022	20	10000	20000	10001	10000	10000	10010
30025	100083	40017	10012	20003	10002	10	20015	10000	30	877164	1279516	30010	20	10001	20003	20	10012	20026	10002	10000	10000	10010
30024	100045	40011	10011	20000	10000	10	20000	10000	30	877164	1279516	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100097	40011	10011	20000	10000	10	20000	10000	30	877288	1279685	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	877164	1279516	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100032	40011	10011	20000	10000	10	20000	10000	30	877164	1279516	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30025	100062	40017	10012	20003	10002	10	20015	10000	30	877251	1279633	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  fjcvtzs w0, d8
  fjcvtzs w1, d8
  fjcvtzs w2, d8
  fjcvtzs w3, d8
  fjcvtzs w4, d8
  fjcvtzs w5, d8
  fjcvtzs w6, d8
  fjcvtzs w7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.1116

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	168934	240101	80101	160000	0	100	160000	0	300	0	2034964	160101	200	0	160008	200	160008	80001	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035316	160101	200	0	160008	200	160008	80001	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035316	160101	200	0	160008	200	160008	80001	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035316	160101	200	0	160008	200	160008	80001	80000	80100
160205	168967	240122	80105	160017	0	100	160031	0	300	0	2035316	160101	200	0	160008	200	160008	80001	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035406	160133	200	0	160048	200	160008	80001	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035316	160101	200	0	160008	200	160008	80001	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035316	160101	200	0	160008	200	160008	80001	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035316	160101	200	0	160008	200	160052	80007	80000	80100
160204	168927	240101	80101	160000	0	100	160001	0	300	0	2035316	160101	200	0	160008	200	160008	80001	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.1116

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160025	168971	240032	80015	160017	10	160031	30	2035109	160012	20	160010	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035476	160050	20	160052	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160044	80005	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160000	80001	80000	80010
160024	168927	240011	80011	160000	10	160000	30	2035311	160010	20	160000	20	160000	80001	80000	80010

FJCVTZS

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations