Icestorm: FMADD (scalar, D) measurements

Code:

  fmadd d0, d0, d1, d2

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000
1004	4033	1001	1	1000	1000	101557	1000	1000	3000	1	1000

Test 2: Latency 1->2

Code:

  fmadd d0, d0, d1, d2

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10205	40066	10105	101	10004	100	10030	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028904	10050	20	10044	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	69	1029251	10080	20	10084	20	30000	11	10000	10

Test 3: Latency 1->3

Code:

  fmadd d0, d1, d0, d2

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10205	40066	10105	101	10004	100	10030	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	0	300	0	1028557	10100	200	0	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->4

Code:

  fmadd d0, d1, d2, d0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	202	30126	2	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100
10204	40033	10101	101	10000	100	10000	300	1028557	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10004	20	30012	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10025	40066	10025	21	10004	20	10030	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10
10024	40033	10021	21	10000	20	10000	70	1028557	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  fmadd d0, d8, d9, d10
  fmadd d1, d8, d9, d10
  fmadd d2, d8, d9, d10
  fmadd d3, d8, d9, d10
  fmadd d4, d8, d9, d10
  fmadd d5, d8, d9, d10
  fmadd d6, d8, d9, d10
  fmadd d7, d8, d9, d10

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40060	80105	101	80004	100	80008	0	300	0	320868	80316	200	0	80220	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320216	80156	200	0	80066	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	240036	1	0	80000	100
80204	40338	80312	101	80211	100	80215	0	300	0	320044	80110	200	0	80014	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	240036	1	0	80000	100
80204	40036	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	240036	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40095	80029	21	80008	20	80012	70	320224	80078	20	80068	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10
80024	40036	80021	21	80000	20	80000	70	320000	80020	20	80000	20	240000	11	80000	10

FMADD (scalar, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations