Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMADD (scalar, H)

Test 1: uops

Code:

  fmadd h0, h0, h1, h2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000
10044033100111000100010155710001000300011000

Test 2: Latency 1->2

Code:

  fmadd h0, h0, h1, h2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100062030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 3: Latency 1->3

Code:

  fmadd h0, h1, h0, h2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420230126210000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028904101302001004420030012110000100
1245757508121041320100127721292100903001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100
102044003310101101100000100100003001028557101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100007010285571002020100062030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010
100244003310021211000020100007010285571002020100002030000111000010

Test 4: Latency 1->4

Code:

  fmadd h0, h1, h2, h0
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010289041013020001004420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10205400661010710310004102100300300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100
10204400331010110110000100100000300010285571010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100244003310021211000020100000700102855710020200100042030012111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010
100244003310021211000020100000700102855710020200100002030000111000010

Test 5: throughput

Count: 8

Code:

  fmadd h0, h8, h9, h10
  fmadd h1, h8, h9, h10
  fmadd h2, h8, h9, h10
  fmadd h3, h8, h9, h10
  fmadd h4, h8, h9, h10
  fmadd h5, h8, h9, h10
  fmadd h6, h8, h9, h10
  fmadd h7, h8, h9, h10
  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400738010710180006100800103003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100
80204400898010510180004100800083003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100
80204400368010510180004100800083003200368010820080012200240036180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244024680029218000820800127032004480030208001620240204118000010
800244003680027218000620800107032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010
800244003680021218000020800007032000080020208000020240000118000010