Icestorm: FMAXNMP (scalar) measurements

Code:

  fmaxnmp d0, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  fmaxnmp d0, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10006	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10006	200	20012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10006	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: throughput

Count: 8

Code:

  fmaxnmp d0, v8.2d
  fmaxnmp d1, v8.2d
  fmaxnmp d2, v8.2d
  fmaxnmp d3, v8.2d
  fmaxnmp d4, v8.2d
  fmaxnmp d5, v8.2d
  fmaxnmp d6, v8.2d
  fmaxnmp d7, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40128	80153	101	80052	100	80056	0	300	0	320236	80158	200	0	80062	200	160122	1	80000	100
80204	40237	80199	103	80096	102	80100	0	300	0	320036	80108	200	0	80012	200	160116	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40034	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100
80204	40106	80153	101	80052	100	80056	0	300	0	320420	80204	200	0	80107	200	160024	1	80000	100
80204	40198	80201	101	80100	100	80104	525	13696	5258	320384	81633	1398	624	80106	200	160024	1	80000	100
80204	40116	80154	101	80053	100	80057	0	300	0	320428	80206	200	0	80109	200	160124	1	80000	100
80204	40106	80153	101	80052	100	80056	0	300	0	320568	80244	200	0	80154	200	160406	1	80000	100
80205	40148	80192	101	80091	100	80103	0	300	0	320044	80110	200	0	80014	200	160024	1	80000	100
80204	40043	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40126	80027	21	80006	20	80010	70	320052	80032	20	80018	20	160036	11	80000	10
80025	40080	80063	21	80042	20	80054	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10

FMAXNMP (scalar)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations