Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FMAXNMV (4H)

Test 1: uops

Code:

  fmaxnmv h0, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->2

Code:

  fmaxnmv h0, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102043003310101101100001001000030076890510100200100062000200081010000100
102043003310101101100001001000030076890510100200100042000200961010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: throughput

Count: 8

Code:

  fmaxnmv h0, v8.4h
  fmaxnmv h1, v8.4h
  fmaxnmv h2, v8.4h
  fmaxnmv h3, v8.4h
  fmaxnmv h4, v8.4h
  fmaxnmv h5, v8.4h
  fmaxnmv h6, v8.4h
  fmaxnmv h7, v8.4h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8020440062801051018000410080008300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001601241080000100
8020440035801071018000610080010300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001600241080000100
8020440035801051018000410080008300320036801082008001220001600241080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8002440227800292180008020800127032004480030208001620160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010
8002440035800212180000020800007032000080020208000020160000118000010